This is series v4 since my previous patches were incomplete with driver
changes missing.
v5 changes.
drop the cd-gpios wp-gpio gpio pin setting, just add the pinctrl
configration to support write protect.
v4 changes.
squash cd-gpios and wp-gpio changes into single patch.
change the subject prefix to "ARM: dts: exynos:"
These changes add UHS-I tuning for dw_mmc-exynos driver.
Rebased on Krzysztof branch next/dt
[0] git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
Anand Moon (6):
ARM: dts: exynos: Added UHS-I bus speed support
ARM: dts: exynos: fix regulator min values of LDO13 for Odroid XU3/XU4
ARM: dts: exynos: update maximum frequency for sdcard to 200MHz
ARM: dts: exynos: Add pin configuration for SD write protect on Odroid
XU3/XU4
ARM: dts: exynos: update maximum frequency for emmc to 200MHz
mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 8 ++++++--
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
4 files changed, 25 insertions(+), 2 deletions(-)
--
2.17.1
Add SD card write-protect pin configuration to be sure that it will be
properly pulled down to indicate write access.
Suggested-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
Changes since v4:
1. Remove cd-gpios and wp-gpios leaving only WP pin configuration (after
Marek Szyprowski feedback).
2. Pull pin down.
3. change the subject and commit message.
Sorry Krzysztof if I have copied your commit message to describe the
changes.
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index dda8ca2d2324..b82af7c89654 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -289,6 +289,13 @@
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
+
+ sd2_wp: sd2-wp {
+ samsung,pins = "gpc4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+ };
};
&pinctrl_2 {
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index a80b6c045154..54811960e322 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -498,7 +498,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
--
2.17.1
set the max-frequency to 200MHz for optimal performace.
Signed-off-by: Anand Moon <[email protected]>
---
This patch is new to this series.
microSD card.
root@odroid:~# sudo cat /sys/kernel/debug/mmc1/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 16 (2.8 ~ 2.9 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 15ab380e5fcf..a80b6c045154 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -501,6 +501,7 @@
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
--
2.17.1
Looking at the schematic sd_2 min/max range from 1.8V/2.8V so fix the
regulator min value to 1.8V. Without these changes sdcard will failed
to detect on booting when UHS-I tuning is enabled.
Signed-off-by: Anand Moon <[email protected]>
---
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/376262.html
Fixed the commit message.
drop the ramp-delay changes.
drop the vmmc-supply/vqmmc-supply changes.
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 0508e6891f41..15ab380e5fcf 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -231,7 +231,7 @@
ldo13_reg: LDO13 {
regulator-name = "vddq_mmc2";
- regulator-min-microvolt = <2800000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
--
2.17.1
Set the max-frequency to 200MHz for optimal performace of eMMC.
Signed-off-by: Anand Moon <[email protected]>
---
eMMC
root@odroid:~# sudo cat /sys/kernel/debug/mmc0/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 7 (1.65 - 1.95 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
---
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index e522edb2bb82..1f2d3987dde1 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -392,6 +392,7 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>;
};
--
2.17.1
Added support for UHS-I bus speed tuning for SDR50, DDR50 SDR104.
Signed-off-by: Anand Moon <[email protected]>
---
---
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/376263.html
Changes from above.
Fix the subject and commit message.
drop sd-uhs-sdr12 and sd-uhs-sdr25 as host driver is not enable as of now.
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2fac4baf1eb4..0508e6891f41 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -503,6 +503,9 @@
cap-sd-highspeed;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
};
&nocp_mem0_0 {
--
2.17.1
Add tuning for sdr and ddr timing for USH-I mode sdr104/sdr50/ddr50
for host controller.
Cc: Jaehoon Chung <[email protected]>
Cc: Marek Szyprowski <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
No changes from previous patch
---
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index ab47b018716a..d46c3439b508 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -253,6 +253,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
if (timing == MMC_TIMING_MMC_HS400) {
dqs |= DATA_STROBE_EN;
strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
+ } else if (timing == MMC_TIMING_UHS_SDR104) {
+ dqs &= 0xffffff00;
} else {
dqs &= ~DATA_STROBE_EN;
}
@@ -312,6 +314,15 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
if (ios->bus_width == MMC_BUS_WIDTH_8)
wanted <<= 1;
break;
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_UHS_SDR50:
+ clksel = (priv->sdr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ clksel = (priv->ddr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
default:
clksel = priv->sdr_timing;
}
--
2.17.1
On 27 September 2018 at 16:07, Anand Moon <[email protected]> wrote:
> This is series v4 since my previous patches were incomplete with driver
> changes missing.
>
> v5 changes.
> drop the cd-gpios wp-gpio gpio pin setting, just add the pinctrl
> configration to support write protect.
>
> v4 changes.
> squash cd-gpios and wp-gpio changes into single patch.
> change the subject prefix to "ARM: dts: exynos:"
>
> These changes add UHS-I tuning for dw_mmc-exynos driver.
>
> Rebased on Krzysztof branch next/dt
> [0] git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
>
> Anand Moon (6):
> ARM: dts: exynos: Added UHS-I bus speed support
> ARM: dts: exynos: fix regulator min values of LDO13 for Odroid XU3/XU4
> ARM: dts: exynos: update maximum frequency for sdcard to 200MHz
> ARM: dts: exynos: Add pin configuration for SD write protect on Odroid
> XU3/XU4
> ARM: dts: exynos: update maximum frequency for emmc to 200MHz
> mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
>
> arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 8 ++++++--
> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
> drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
> 4 files changed, 25 insertions(+), 2 deletions(-)
>
> --
> 2.17.1
>
Anand,
I have applied the mmc patch for next, thanks!
In regards to the DTS changes, I assume the soc maintainers will pick
them up, but maybe you need to resend them separately.
Kind regards
Uffe
On Thu, Sep 27, 2018 at 02:07:33PM +0000, Anand Moon wrote:
> Added support for UHS-I bus speed tuning for SDR50, DDR50 SDR104.
>
Thanks, applied.
Best regards,
Krzysztof
On Thu, Sep 27, 2018 at 02:07:34PM +0000, Anand Moon wrote:
> Looking at the schematic sd_2 min/max range from 1.8V/2.8V so fix the
> regulator min value to 1.8V. Without these changes sdcard will failed
> to detect on booting when UHS-I tuning is enabled.
>
Thanks, applied.
Best regards,
Krzysztof
On Thu, Sep 27, 2018 at 02:07:35PM +0000, Anand Moon wrote:
> set the max-frequency to 200MHz for optimal performace.
>
Thanks, applied.
Best regards,
Krzysztof
On Thu, Sep 27, 2018 at 02:07:37PM +0000, Anand Moon wrote:
> Set the max-frequency to 200MHz for optimal performace of eMMC.
>
Thanks, applied.
Best regards,
Krzysztof
On Thu, Sep 27, 2018 at 02:07:36PM +0000, Anand Moon wrote:
> Add SD card write-protect pin configuration to be sure that it will be
> properly pulled down to indicate write access.
>
> Suggested-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> Changes since v4:
> 1. Remove cd-gpios and wp-gpios leaving only WP pin configuration (after
> Marek Szyprowski feedback).
> 2. Pull pin down.
> 3. change the subject and commit message.
> Sorry Krzysztof if I have copied your commit message to describe the
> changes.
Thanks, applied.
Best regards,
Krzysztof