Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.
Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index e70e425f26f5..9d6c88064158 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -402,10 +402,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
/*
* Read efuse register having TUNE2/1 parameter's high nibble.
- * If efuse register shows value as 0x0, or if we fail to find
- * a valid efuse register settings, then use default value
- * as 0xB for high nibble that we have already set while
- * configuring phy.
+ * If efuse register shows value as 0x0 (indicating value is not
+ * fused), or if we fail to find a valid efuse register setting,
+ * then use default value for high nibble that we have already
+ * set while configuring the phy.
*/
val = nvmem_cell_read(qphy->cell, NULL);
if (IS_ERR(val) || !val[0]) {
@@ -415,12 +415,13 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
/* Fused TUNE1/2 value is the higher nibble only */
if (cfg->update_tune1_with_efuse)
- qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
- val[0] << 0x4);
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
+ val[0] << HSTX_TRIM_SHIFT,
+ HSTX_TRIM_MASK);
else
- qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
- val[0] << 0x4);
-
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
+ val[0] << HSTX_TRIM_SHIFT,
+ HSTX_TRIM_MASK);
}
static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: Manu Gautam <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 9d6c88064158..69c92843eb3b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.autoresume_en = BIT(0),
+ .update_tune1_with_efuse = true,
};
static const char * const qusb2_phy_vreg_names[] = {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Quoting Manu Gautam (2018-10-16 00:22:06)
> Fix HSTX_TRIM tuning logic which instead of using fused value
> as HSTX_TRIM, incorrectly performs bitwise OR operation with
> existing default value.
>
> Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
> Signed-off-by: Manu Gautam <[email protected]>
> Reviewed-by: Douglas Anderson <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Manu Gautam (2018-10-16 00:22:07)
> Tune1 register on sdm845 is used to update HSTX_TRIM with fused
> setting. Enable same by specifying update_tune1_with_efuse flag
> for sdm845, otherwise driver ends up programming tune2 register.
>
> Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
> Signed-off-by: Manu Gautam <[email protected]>
> Reviewed-by: Douglas Anderson <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
On 2018-10-25 11:46, Vivek Gautam wrote:
> Hi Manu,
>
> On 10/16/2018 12:52 PM, Manu Gautam wrote:
>
>> Fix HSTX_TRIM tuning logic which instead of using fused value
>> as HSTX_TRIM, incorrectly performs bitwise OR operation with
>> existing default value.
>>
>> Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on
>> Qcom chips")
>> Signed-off-by: Manu Gautam <[email protected]>
>> Reviewed-by: Douglas Anderson <[email protected]>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qusb2.c | 19 ++++++++++---------
>> 1 file changed, 10 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index e70e425f26f5..9d6c88064158 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -402,10 +402,10 @@ static void qusb2_phy_set_tune2_param(struct
>> qusb2_phy *qphy)
>>
>> /*
>> * Read efuse register having TUNE2/1 parameter's high nibble.
>> - * If efuse register shows value as 0x0, or if we fail to find
>> - * a valid efuse register settings, then use default value
>> - * as 0xB for high nibble that we have already set while
>> - * configuring phy.
>> + * If efuse register shows value as 0x0 (indicating value is
>> not
>> + * fused), or if we fail to find a valid efuse register
>> setting,
>> + * then use default value for high nibble that we have already
>> + * set while configuring the phy.
>> */
>> val = nvmem_cell_read(qphy->cell, NULL);
>> if (IS_ERR(val) || !val[0]) {
>> @@ -415,12 +415,13 @@ static void qusb2_phy_set_tune2_param(struct
>> qusb2_phy *qphy)
>>
>> /* Fused TUNE1/2 value is the higher nibble only */
>> if (cfg->update_tune1_with_efuse)
>> - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
>> - val[0] << 0x4);
>> + qusb2_write_mask(qphy->base,
>> cfg->regs[QUSB2PHY_PORT_TUNE1],
>> + val[0] << HSTX_TRIM_SHIFT,
>> + HSTX_TRIM_MASK);
>> else
>> - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
>> - val[0] << 0x4);
>> -
>> + qusb2_write_mask(qphy->base,
>> cfg->regs[QUSB2PHY_PORT_TUNE2],
>> + val[0] << HSTX_TRIM_SHIFT,
>> + HSTX_TRIM_MASK);
>> }
>>
>> static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
>
> Thanks for the patch.
> Acked-by: Vivek Gautam <[email protected]>
>
My bad. Didn't notice the HTML mode. Resending, so that it reaches to
lists as well.
Thanks
Vivek
> Regards
> Vivek