GPIOs 0 through 3 and 81 through 84 are configured to not be accessible
from the application CPUs. Mark them as reserved to allow the MSM8998
MTP to boot after the introduction of 3edfb7bd76bd ("gpiolib: Show
correct direction from the beginning").
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index b4276da1fb0d..11fd1fe8bdb5 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -241,3 +241,7 @@
};
};
};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+};
--
2.18.0
On 10/29/2018 11:45 PM, Bjorn Andersson wrote:
> GPIOs 0 through 3 and 81 through 84 are configured to not be accessible
> from the application CPUs. Mark them as reserved to allow the MSM8998
> MTP to boot after the introduction of 3edfb7bd76bd ("gpiolib: Show
> correct direction from the beginning").
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> index b4276da1fb0d..11fd1fe8bdb5 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
> @@ -241,3 +241,7 @@
> };
> };
> };
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <81 4>;
> +};
>
Does Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
need to be updated? Seems like the majority of the other qcom pinctrl
bindings docs mention that gpio-reserved-ranges is optional.
In any case,
Reviewed-by: Jeffrey Hugo <[email protected]>
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.