From: Hou Zhiqiang <[email protected]>
This patch set is to add prefetchable memory range support, patch 5/5.
Patch 1/5 and 2/5 are to initialize the number of viewport for
layerscape PCIe.
BTW, fix 2 bugs, see patch 3/5 and 4/5.
Hou Zhiqiang (5):
ARM: dts: ls1021a: add num-viewport property for PCIe DT nodes
arm64: dts: layerscape: add num-viewport property for PCIe DT nodes
PCI: dwc: fix potential memory leak
PCI: dwc: fix 4GiB outbound window size truncated to zero issue
PCI: dwc: add prefetchable memory range support
arch/arm/boot/dts/ls1021a.dtsi | 2 +
.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 +
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 +
.../pci/controller/dwc/pcie-designware-host.c | 135 +++++++++++++-----
drivers/pci/controller/dwc/pcie-designware.c | 4 +-
drivers/pci/controller/dwc/pcie-designware.h | 11 +-
9 files changed, 128 insertions(+), 38 deletions(-)
--
2.17.1
From: Hou Zhiqiang <[email protected]>
To avoid memory leak on error return of the adjacent function
devm_of_pci_get_host_bridge_resources(), change to use
devm_pci_alloc_host_bridge() to allocate host bridge structure,
then it will be managed automatically.
Fixes: 295aeb98a322 ("PCI: designware: Convert PCI scan API to
pci_scan_root_bus_bridge()")
Signed-off-by: Hou Zhiqiang <[email protected]>
---
V3:
- Changed to use devm_* to allocate host bridge.
- Added Fixes info.
.../pci/controller/dwc/pcie-designware-host.c | 28 ++++++++-----------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 29a05759a294..33b5a3815d24 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -346,7 +346,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(dev, "Missing *config* reg space\n");
}
- bridge = pci_alloc_host_bridge(0);
+ bridge = devm_pci_alloc_host_bridge(dev, 0);
if (!bridge)
return -ENOMEM;
@@ -357,7 +357,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
ret = devm_request_pci_bus_resources(dev, &bridge->windows);
if (ret)
- goto error;
+ return ret;
/* Get the I/O and memory ranges from DT */
resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
@@ -401,8 +401,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
resource_size(pp->cfg));
if (!pci->dbi_base) {
dev_err(dev, "Error with ioremap\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -413,8 +412,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg0_base, pp->cfg0_size);
if (!pp->va_cfg0_base) {
dev_err(dev, "Error with ioremap in function\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -424,8 +422,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg1_size);
if (!pp->va_cfg1_base) {
dev_err(dev, "Error with ioremap\n");
- ret = -ENOMEM;
- goto error;
+ return -ENOMEM;
}
}
@@ -448,14 +445,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->num_vectors == 0) {
dev_err(dev,
"Invalid number of vectors\n");
- goto error;
+ return -EINVAL;
}
}
if (!pp->ops->msi_host_init) {
ret = dw_pcie_allocate_domains(pp);
if (ret)
- goto error;
+ return ret;
if (pp->msi_irq)
irq_set_chained_handler_and_data(pp->msi_irq,
@@ -464,14 +461,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
} else {
ret = pp->ops->msi_host_init(pp);
if (ret < 0)
- goto error;
+ return ret;
}
}
if (pp->ops->host_init) {
ret = pp->ops->host_init(pp);
if (ret)
- goto error;
+ return ret;
}
pp->root_bus_nr = pp->busn->start;
@@ -485,7 +482,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
ret = pci_scan_root_bus_bridge(bridge);
if (ret)
- goto error;
+ return ret;
bus = bridge->bus;
@@ -499,11 +496,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
- return 0;
-error:
- pci_free_host_bridge(bridge);
- return ret;
+ return 0;
}
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
--
2.17.1
From: Hou Zhiqiang <[email protected]>
Add num-viewport property for PCIe DT nodes to specify how many
viewports are implemented.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
V3:
- New patch
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++++
5 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 21f2b3ba6b58..7ce0aa52292c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -486,6 +486,7 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
+ num-viewport = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 760d510d78de..f42368afeea9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -673,6 +673,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -699,6 +700,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -725,6 +727,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 64d334c6b0b4..10be89168793 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -642,6 +642,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -668,6 +669,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -694,6 +696,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <2>;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 9deb9cb83046..7d303bd40047 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -523,6 +523,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -548,6 +549,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -573,6 +575,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <8>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 5732e3b48be7..4bb9aa2dd8b2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -640,6 +640,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
@@ -662,6 +663,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
@@ -684,6 +686,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <8>;
+ num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
@@ -706,6 +709,7 @@
device_type = "pci";
dma-coherent;
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
--
2.17.1
From: Hou Zhiqiang <[email protected]>
The current code only support non-prefetchable memory range,
as the non-prefetchable memory range must not be greater than
4GiB, one viewport can cover it, which supports upto 4GiB.
To support prefetchable memory range, which is upto 64-bit
memory space and can be greater than 4GiB, so we need multiple
viewports. And added separate vars to store prefetchable memory
range info to prevent overriding the non-prefetchable memory
range info.
And this patch explicitly assigned the last (if there are only
2 viewports) or last 2 viewports for CFG and I/O windows and the
rests for MEM windows.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
V3:
- Changed back to get num-viewport from DTS.
- Added print info upon non-pref memory truncated.
- Corrected typo.
.../pci/controller/dwc/pcie-designware-host.c | 107 +++++++++++++++---
drivers/pci/controller/dwc/pcie-designware.h | 7 ++
2 files changed, 97 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 33b5a3815d24..2d1dd3dba1ba 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -346,6 +346,28 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(dev, "Missing *config* reg space\n");
}
+ ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
+ if (ret || pci->num_viewport < 2)
+ pci->num_viewport = 2;
+
+ /*
+ * if there are only 2 viewports, assign the last viewport for
+ * both CFG and IO window, otherwise assign the last 2 viewport
+ * for CFG and IO window specific. And the rest viewports are
+ * assigned to MEM windows.
+ */
+ if (pci->num_viewport == 2) {
+ pp->cfg_idx = pp->io_idx = PCIE_ATU_REGION_INDEX1;
+ pp->mem_wins = 1;
+ } else {
+ pp->cfg_idx = pci->num_viewport - 1;
+ pp->io_idx = pci->num_viewport - 2;
+ pp->mem_wins = pci->num_viewport - 2;
+ }
+
+ dev_dbg(dev, "CFG win id: %d, I/O win id: %d, Total MEM win: %d\n",
+ pp->cfg_idx, pp->io_idx, pp->mem_wins);
+
bridge = devm_pci_alloc_host_bridge(dev, 0);
if (!bridge)
return -ENOMEM;
@@ -377,10 +399,20 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
break;
case IORESOURCE_MEM:
- pp->mem = win->res;
- pp->mem->name = "MEM";
- pp->mem_size = resource_size(pp->mem);
- pp->mem_bus_addr = pp->mem->start - win->offset;
+ if (win->res->flags & IORESOURCE_PREFETCH) {
+ pp->mem_pref = win->res;
+ pp->mem_pref->name = "MEM pref";
+ pp->mem_pref_size = resource_size(pp->mem_pref);
+ pp->mem_pref_bus_addr = pp->mem_pref->start -
+ win->offset;
+ pp->mem_pref_base = pp->mem_pref->start;
+ } else {
+ pp->mem = win->res;
+ pp->mem->name = "MEM";
+ pp->mem_size = resource_size(pp->mem);
+ pp->mem_bus_addr = pp->mem->start - win->offset;
+ pp->mem_base = pp->mem->start;
+ }
break;
case 0:
pp->cfg = win->res;
@@ -405,8 +437,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp->mem_base = pp->mem->start;
-
if (!pp->va_cfg0_base) {
pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
pp->cfg0_base, pp->cfg0_size);
@@ -527,12 +557,12 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ dw_pcie_prog_outbound_atu(pci, pp->cfg_idx,
type, cpu_addr,
busdev, cfg_size);
ret = dw_pcie_read(va_cfg_base + where, size, val);
- if (pci->num_viewport <= 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ if (pp->cfg_idx == pp->io_idx)
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -566,12 +596,12 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ dw_pcie_prog_outbound_atu(pci, pp->cfg_idx,
type, cpu_addr,
busdev, cfg_size);
ret = dw_pcie_write(va_cfg_base + where, size, val);
- if (pci->num_viewport <= 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ if (pp->cfg_idx == pp->io_idx)
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -645,6 +675,9 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val, ctrl, num_ctrls;
+ u64 unmapped_size, base, win_size;
+ phys_addr_t bus_addr;
+ int i;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
dw_pcie_setup(pci);
@@ -693,13 +726,53 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dev_dbg(pci->dev, "iATU unroll: %s\n",
pci->iatu_unroll_enabled ? "enabled" : "disabled");
+ /*
+ * The maximum region size is 4 GB, and a region
+ * must not cross a 4 GB boundary.
+ */
+ win_size = SZ_4G - (pp->mem_base & (SZ_4G - 1));
+ win_size = min(win_size, pp->mem_size);
+ if (win_size < pp->mem_size)
+ dev_info(pci->dev,
+ "iATU: non-pref MEM size is truncated to 0x%llx\n",
+ win_size);
+
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM, pp->mem_base,
- pp->mem_bus_addr, pp->mem_size);
- if (pci->num_viewport > 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
- PCIE_ATU_TYPE_IO, pp->io_base,
- pp->io_bus_addr, pp->io_size);
+ pp->mem_bus_addr, win_size);
+ dev_dbg(pci->dev,
+ "iATU: non-pref MEM: win = %d: base = 0x%llx, bus_addr = %pa, size = 0x%llx\n",
+ 0, pp->mem_base, &pp->mem_bus_addr, win_size);
+
+ /*
+ * Prefetchable memory range can be 64bit space,
+ * so may need multiple viewports.
+ */
+ unmapped_size = pp->mem_pref_size;
+ base = pp->mem_pref_base;
+ bus_addr = pp->mem_pref_bus_addr;
+ for (i = PCIE_ATU_REGION_INDEX1;
+ unmapped_size > 0 && i < pp->mem_wins; i++) {
+ win_size = SZ_4G - (base & (SZ_4G - 1));
+ win_size = min(win_size, unmapped_size);
+ dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
+ base, bus_addr, win_size);
+ dev_dbg(pci->dev,
+ "iATU: pref MEM: win = %d: base = 0x%llx, bus_addr = %pa, size = 0x%llx\n",
+ i, base, &bus_addr, win_size);
+
+ base += win_size;
+ bus_addr += win_size;
+ unmapped_size -= win_size;
+ }
+
+ if (unmapped_size > 0)
+ dev_info(pci->dev,
+ "iATU: can't cover pref memory range\n");
+
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx, PCIE_ATU_TYPE_IO,
+ pp->io_base, pp->io_bus_addr,
+ pp->io_size);
}
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 25604387d13e..1e87f18bc417 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -152,15 +152,22 @@ struct pcie_port {
u64 cfg1_base;
void __iomem *va_cfg1_base;
u32 cfg1_size;
+ u32 cfg_idx;
resource_size_t io_base;
phys_addr_t io_bus_addr;
u32 io_size;
+ u32 io_idx;
u64 mem_base;
phys_addr_t mem_bus_addr;
u64 mem_size;
+ phys_addr_t mem_pref_base;
+ pci_bus_addr_t mem_pref_bus_addr;
+ u64 mem_pref_size;
+ u32 mem_wins;
struct resource *cfg;
struct resource *io;
struct resource *mem;
+ struct resource *mem_pref;
struct resource *busn;
int irq;
const struct dw_pcie_host_ops *ops;
--
2.17.1
From: Hou Zhiqiang <[email protected]>
Add num-viewport property for PCIe DT nodes to specify how many
viewports are implemented.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
V3:
- New patch
arch/arm/boot/dts/ls1021a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index b769e0e40553..b455acc7afb4 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -726,6 +726,7 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -750,6 +751,7 @@
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
+ num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
--
2.17.1
From: Hou Zhiqiang <[email protected]>
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Fixes: 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos")
Signed-off-by: Hou Zhiqiang <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
---
V3:
- No change
drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2153956a0b20..7ac5989c23ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -106,7 +106,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
int type, u64 cpu_addr,
- u64 pci_addr, u32 size)
+ u64 pci_addr, u64 size)
{
u32 retries, val;
@@ -141,7 +141,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u32 size)
+ u64 cpu_addr, u64 pci_addr, u64 size)
{
u32 retries, val;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0989d880ac46..25604387d13e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -157,7 +157,7 @@ struct pcie_port {
u32 io_size;
u64 mem_base;
phys_addr_t mem_bus_addr;
- u32 mem_size;
+ u64 mem_size;
struct resource *cfg;
struct resource *io;
struct resource *mem;
@@ -242,7 +242,7 @@ int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
- u32 size);
+ u64 size);
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
u64 cpu_addr, enum dw_pcie_as_type as_type);
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
--
2.17.1
On Tue, Dec 18, 2018 at 04:19:26AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <[email protected]>
>
> Add num-viewport property for PCIe DT nodes to specify how many
> viewports are implemented.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
Applied, thanks.
On Tue, Dec 18, 2018 at 04:19:32AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <[email protected]>
>
> Add num-viewport property for PCIe DT nodes to specify how many
> viewports are implemented.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
Applied, thanks.