There are HSRUN mode clock mux and divider in SCG1 module,
and SMC1 can control i.MX7ULP CPU to run in RUN mode or
HSRUN mode, the mode switch bits are actually a clock mux,
add these clocks for clock driver and dtb to use.
Signed-off-by: Anson Huang <[email protected]>
---
include/dt-bindings/clock/imx7ulp-clock.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 008c5ee..21d872e 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -54,8 +54,10 @@
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
#define IMX7ULP_CLK_SPLL_BUS_CLK 43
+#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
+#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
-#define IMX7ULP_CLK_SCG1_END 44
+#define IMX7ULP_CLK_SCG1_END 46
/* PCC2 */
#define IMX7ULP_CLK_DMA1 0
@@ -106,4 +108,9 @@
#define IMX7ULP_CLK_PCC3_END 16
+/* SMC1 */
+#define IMX7ULP_CLK_ARM 0
+
+#define IMX7ULP_CLK_SMC1_END 1
+
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.7.4
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.
Latest clock tree in RUN mode as below:
firc 0 0 0 48000000 0 0 50000
firc_bus_clk 0 0 0 48000000 0 0 50000
hsrun_scs_sel 0 0 0 48000000 0 0 50000
hsrun_divcore 0 0 0 48000000 0 0 50000
sosc 3 3 3 24000000 0 0 50000
spll_pre_sel 1 1 1 24000000 0 0 50000
spll_pre_div 1 1 2 24000000 0 0 50000
spll 1 1 2 528000000 0 0 50000
spll_pfd0 1 1 1 500210526 0 0 50000
spll_pfd_sel 1 1 0 500210526 0 0 50000
spll_sel 1 1 0 500210526 0 0 50000
scs_sel 1 1 0 500210526 0 0 50000
divcore 1 1 0 500210526 0 0 50000
arm 1 1 0 500210526 0 0 50000
Signed-off-by: Anson Huang <[email protected]>
---
drivers/clk/imx/clk-imx7ulp.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 3b7507f..4e18f62 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -29,6 +29,7 @@ static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
static const struct clk_div_table ulp_div_table[] = {
@@ -102,10 +103,12 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
/* scs/ddr/nic select different clock source requires that clock to be enabled first */
clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
+ clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
- clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
+ clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);
clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
0, ulp_div_table, &imx_ccm_lock);
@@ -218,3 +221,29 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
}
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
+
+static void __init imx7ulp_clk_smc1_init(struct device_node *np)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ void __iomem *base;
+
+ clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
+ IMX7ULP_CLK_SMC1_END, GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_SMC1_END;
+ clks = clk_data->hws;
+
+ /* SMC1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+}
+CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init);
--
2.7.4
i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.
Signed-off-by: Anson Huang <[email protected]>
---
This patch is based on top of path series: [V5,1/6] dt-bindings: fsl: add compatible for imx7ulp evk,
https://patchwork.kernel.org/patch/10677263/
---
arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b275..b86daf7 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
};
- smc1: smc1@40410000 {
+ smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+ <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+ clock-names = "divcore", "hsrun_divcore";
};
pcc3: clock-controller@40b30000 {
--
2.7.4
Quoting Anson Huang (2018-12-07 02:03:29)
> There are HSRUN mode clock mux and divider in SCG1 module,
> and SMC1 can control i.MX7ULP CPU to run in RUN mode or
> HSRUN mode, the mode switch bits are actually a clock mux,
> add these clocks for clock driver and dtb to use.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
Applied to clk-next
Quoting Anson Huang (2018-12-07 02:03:34)
> i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
> or HSRUN mode, it is controlled in SMC1 module. The RUN
> mode and HSRUN mode will use different clock source for
> ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
> mode, so the control bits in SMC1 module can be abstracted
> as a HW clock mux, this patch adds HSRUN mode related
> clocks in SCG1 module and adds "arm" clock in SMC1 module
> to support RUN mode and HSRUN mode switch.
>
> Latest clock tree in RUN mode as below:
>
> firc 0 0 0 48000000 0 0 50000
> firc_bus_clk 0 0 0 48000000 0 0 50000
> hsrun_scs_sel 0 0 0 48000000 0 0 50000
> hsrun_divcore 0 0 0 48000000 0 0 50000
>
> sosc 3 3 3 24000000 0 0 50000
> spll_pre_sel 1 1 1 24000000 0 0 50000
> spll_pre_div 1 1 2 24000000 0 0 50000
> spll 1 1 2 528000000 0 0 50000
> spll_pfd0 1 1 1 500210526 0 0 50000
> spll_pfd_sel 1 1 0 500210526 0 0 50000
> spll_sel 1 1 0 500210526 0 0 50000
> scs_sel 1 1 0 500210526 0 0 50000
> divcore 1 1 0 500210526 0 0 50000
> arm 1 1 0 500210526 0 0 50000
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
Applied to clk-next
On Fri, Dec 07, 2018 at 10:03:39AM +0000, Anson Huang wrote:
> i.MX7ULP can switch CPU between RUN mode and HSRUN mode
> by programming SMC1 register, different clock sources
> will be used for CPU in different modes, so SMC1 can be
> abstracted as a clock controller for CPU clock switch,
> this patch adds support for it.
>
> Signed-off-by: Anson Huang <[email protected]>
Applied, thanks.