Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
pinctrl0: pinctrl@ff180000 {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
};
};
};
};
};
Nava kishore Manne (3):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Rajan Vaja (3):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++++++++++++++++++
.../power/reset/xlnx,zynqmp-power.txt | 25 ++
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 ++++
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h | 130 +++++++++
8 files changed, 615 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
--
2.18.0
From: Rajan Vaja <[email protected]>
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes for v3:
-None.
.../power/reset/xlnx,zynqmp-power.txt | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index 000000000000..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+--------------------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+--------------------------------------------------------------------
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible: Must contain: "xlnx,zynqmp-power"
+ - interrupts: Interrupt specifier
+
+-------
+Example
+-------
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ };
+};
--
2.18.0
From: Rajan Vaja <[email protected]>
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes for v3:
-None.
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 ++++++++++++++++
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++
2 files changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index 000000000000..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+-----------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+-----------------------------------------------------------
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+-------
+Example
+-------
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ ...
+ #power-domain-cells = <1>;
+ ...
+ };
+};
+
+sata {
+ ...
+ power-domains = <&zynqmp_firmware 2>;
+ ...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 000000000000..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define PD_USB_0 0
+#define PD_USB_1 1
+#define PD_SATA 2
+#define PD_SPI_0 3
+#define PD_SPI_1 4
+#define PD_UART_0 5
+#define PD_UART_1 6
+#define PD_ETH_0 7
+#define PD_ETH_1 8
+#define PD_ETH_2 9
+#define PD_ETH_3 10
+#define PD_I2C_0 11
+#define PD_I2C_1 12
+#define PD_DP 13
+#define PD_GDMA 14
+#define PD_ADMA 15
+#define PD_TTC_0 16
+#define PD_TTC_1 17
+#define PD_TTC_2 18
+#define PD_TTC_3 19
+#define PD_SD_0 20
+#define PD_SD_1 21
+#define PD_NAND 22
+#define PD_QSPI 23
+#define PD_GPIO 24
+#define PD_CAN_0 25
+#define PD_CAN_1 26
+#define PD_PCIE 27
+#define PD_GPU 28
+
+#endif
--
2.18.0
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v3:
-Removed PCAP as a child node to the FW and Created
an independent node since PCAP driver is a consumer
not a provider.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
--
2.18.0
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v3:
-Added nvmem node as child of FW. Since nvmem driver is a provider.
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index 000000000000..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--------------------------------------------------------------------------
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+-------
+ Example
+-------
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0