2019-01-28 05:03:21

by Mandal, Purna Chandra

Subject: [PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

cadence-quadspi controller allows upto eight bytes of data to
be written in software Triggered Instruction generator (STIG) mode
of operation. Lower 4 bytes are written through writedatalower and
upper 4 bytes by writedataupper register.

This patch allows all the 8 bytes to be written.

Signed-off-by: Purna Chandra Mandal <[email protected]>
---

drivers/mtd/spi-nor/cadence-quadspi.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 04cedd3a2bf6..7f78f9409ddd 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
unsigned int data;
+ u32 write_len;
int ret;

- if (n_tx > 4 || (n_tx && !txbuf)) {
+ if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(nor->dev,
"Invalid input argument, cmdlen %d txbuf 0x%p\n",
n_tx, txbuf);
@@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
data = 0;
- memcpy(&data, txbuf, n_tx);
+ write_len = (n_tx > 4) ? 4 : n_tx;
+ memcpy(&data, txbuf, write_len);
+ txbuf += write_len;
writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
- }

+ if (n_tx > 4) {
+ data = 0;
+ write_len = n_tx - 4;
+ memcpy(&data, txbuf, write_len);
+ writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
+ }
+ }
ret = cqspi_exec_flash_cmd(cqspi, reg);
return ret;
}
--
2.13.0

2019-02-03 12:22:01

by Tudor Ambarus

Subject: Re: [PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

+ Vignesh

On 01/28/2019 07:02 AM, Purna Chandra Mandal wrote:
> cadence-quadspi controller allows upto eight bytes of data to
> be written in software Triggered Instruction generator (STIG) mode
> of operation. Lower 4 bytes are written through writedatalower and
> upper 4 bytes by writedataupper register.
>
> This patch allows all the 8 bytes to be written.
>
> Signed-off-by: Purna Chandra Mandal <[email protected]>

Looks good for me:
Reviewed-by: Tudor Ambarus <[email protected]>

Vignesh, can we have your R-b or T-b tag?

Cheers,
ta

> ---
>
> drivers/mtd/spi-nor/cadence-quadspi.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 04cedd3a2bf6..7f78f9409ddd 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
> void __iomem *reg_base = cqspi->iobase;
> unsigned int reg;
> unsigned int data;
> + u32 write_len;
> int ret;
>
> - if (n_tx > 4 || (n_tx && !txbuf)) {
> + if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
> dev_err(nor->dev,
> "Invalid input argument, cmdlen %d txbuf 0x%p\n",
> n_tx, txbuf);
> @@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
> reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
> << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
> data = 0;
> - memcpy(&data, txbuf, n_tx);
> + write_len = (n_tx > 4) ? 4 : n_tx;
> + memcpy(&data, txbuf, write_len);
> + txbuf += write_len;
> writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
> - }
>
> + if (n_tx > 4) {
> + data = 0;
> + write_len = n_tx - 4;
> + memcpy(&data, txbuf, write_len);
> + writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
> + }
> + }
> ret = cqspi_exec_flash_cmd(cqspi, reg);
> return ret;
> }
>

2019-02-04 14:29:03

by Vignesh Raghavendra

Subject: Re: [PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

Hi,

On 03/02/19 5:50 PM, [email protected] wrote:
> + Vignesh
>

Thanks for looping in.

> On 01/28/2019 07:02 AM, Purna Chandra Mandal wrote:
>> cadence-quadspi controller allows upto eight bytes of data to
>> be written in software Triggered Instruction generator (STIG) mode
>> of operation. Lower 4 bytes are written through writedatalower and
>> upper 4 bytes by writedataupper register.
>>
>> This patch allows all the 8 bytes to be written.
>>

Code as such looks fine. But, how was this tested? How can I trigger
this new code path with current linux-next? AFAICS, STIG mode write is
used to in nor->write_reg() path, and I dont see any nor->write_reg()
call with >4bytes len.

>> Signed-off-by: Purna Chandra Mandal <[email protected]>
>
> Looks good for me:
> Reviewed-by: Tudor Ambarus <[email protected]>
>
> Vignesh, can we have your R-b or T-b tag?
>
> Cheers,
> ta
>
>> ---
>>
>> drivers/mtd/spi-nor/cadence-quadspi.c | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 04cedd3a2bf6..7f78f9409ddd 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>> void __iomem *reg_base = cqspi->iobase;
>> unsigned int reg;
>> unsigned int data;
>> + u32 write_len;
>> int ret;
>>
>> - if (n_tx > 4 || (n_tx && !txbuf)) {
>> + if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
>> dev_err(nor->dev,
>> "Invalid input argument, cmdlen %d txbuf 0x%p\n",
>> n_tx, txbuf);
>> @@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>> reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
>> << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
>> data = 0;
>> - memcpy(&data, txbuf, n_tx);
>> + write_len = (n_tx > 4) ? 4 : n_tx;
>> + memcpy(&data, txbuf, write_len);
>> + txbuf += write_len;
>> writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
>> - }
>>
>> + if (n_tx > 4) {
>> + data = 0;
>> + write_len = n_tx - 4;
>> + memcpy(&data, txbuf, write_len);
>> + writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
>> + }
>> + }
>> ret = cqspi_exec_flash_cmd(cqspi, reg);
>> return ret;
>> }
>>

--
Regards
Vignesh

2019-02-05 07:21:28

by Mandal, Purna Chandra

Subject: Re: [PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

On 04-Feb-19 7:07 PM, Vignesh R wrote:
> Hi,
>
> On 03/02/19 5:50 PM, [email protected] wrote:
>> + Vignesh
>>
>
> Thanks for looping in.
>
>> On 01/28/2019 07:02 AM, Purna Chandra Mandal wrote:
>>> cadence-quadspi controller allows upto eight bytes of data to
>>> be written in software Triggered Instruction generator (STIG) mode
>>> of operation. Lower 4 bytes are written through writedatalower and
>>> upper 4 bytes by writedataupper register.
>>>
>>> This patch allows all the 8 bytes to be written.
>>>
>
> Code as such looks fine. But, how was this tested? How can I trigger
> this new code path with current linux-next? AFAICS, STIG mode write is
> used to in nor->write_reg() path, and I dont see any nor->write_reg()
> call with >4bytes len.
Currently there is no linux user of write_reg() for write_len > 4byte.

For volatile and non-volatile sector locking [1], we have one out of
tree implementation and that is specific to flash chip "mt25qu02g". In
this implementation we need additional sector address (4 byte) to be
provided for each lock-bit write/erase operation. So total write len in
write_reg() will be 6 bytes (=1 for opcode, 4 for sect addr, 1 for
data). We are finalizing the patch for review.

Since cadence qspi controller do support the 8-byte read/write in STIG
mode, I have tried here to enable that in write_reg(), similar to
read_reg().

[1]
https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf

>
>>> Signed-off-by: Purna Chandra Mandal <[email protected]>
>>
>> Looks good for me:
>> Reviewed-by: Tudor Ambarus <[email protected]>
>>
>> Vignesh, can we have your R-b or T-b tag?
>>
>> Cheers,
>> ta
>>
>>> ---
>>>
>>> drivers/mtd/spi-nor/cadence-quadspi.c | 15 ++++++++++++---
>>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>>> index 04cedd3a2bf6..7f78f9409ddd 100644
>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>>> @@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>>> void __iomem *reg_base = cqspi->iobase;
>>> unsigned int reg;
>>> unsigned int data;
>>> + u32 write_len;
>>> int ret;
>>>
>>> - if (n_tx > 4 || (n_tx && !txbuf)) {
>>> + if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
>>> dev_err(nor->dev,
>>> "Invalid input argument, cmdlen %d txbuf 0x%p\n",
>>> n_tx, txbuf);
>>> @@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>>> reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
>>> << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
>>> data = 0;
>>> - memcpy(&data, txbuf, n_tx);
>>> + write_len = (n_tx > 4) ? 4 : n_tx;
>>> + memcpy(&data, txbuf, write_len);
>>> + txbuf += write_len;
>>> writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
>>> - }
>>>
>>> + if (n_tx > 4) {
>>> + data = 0;
>>> + write_len = n_tx - 4;
>>> + memcpy(&data, txbuf, write_len);
>>> + writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
>>> + }
>>> + }
>>> ret = cqspi_exec_flash_cmd(cqspi, reg);
>>> return ret;
>>> }
>>>
>

2019-02-05 10:29:01

by Vignesh Raghavendra

Subject: Re: [PATCH] mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

On 05/02/19 12:30 PM, Mandal, Purna Chandra wrote:
>
>
> On 04-Feb-19 7:07 PM, Vignesh R wrote:
>> Hi,
>>
>> On 03/02/19 5:50 PM, [email protected] wrote:
>>> + Vignesh
>>>
>>
>> Thanks for looping in.
>>
>>> On 01/28/2019 07:02 AM, Purna Chandra Mandal wrote:
>>>> cadence-quadspi controller allows upto eight bytes of data to
>>>> be written in software Triggered Instruction generator (STIG) mode
>>>> of operation. Lower 4 bytes are written through writedatalower and
>>>> upper 4 bytes by writedataupper register.
>>>>
>>>> This patch allows all the 8 bytes to be written.
>>>>
>>
>> Code as such looks fine. But, how was this tested? How can I trigger
>> this new code path with current linux-next? AFAICS, STIG mode write is
>> used to in nor->write_reg() path, and I dont see any nor->write_reg()
>> call with >4bytes len.
> Currently there is no linux user of write_reg() for write_len > 4byte.
>
> For volatile and non-volatile sector locking [1], we have one out of
> tree implementation and that is specific to flash chip "mt25qu02g". In
> this implementation we need additional sector address (4 byte) to be
> provided for each lock-bit write/erase operation. So total write len in
> write_reg() will be 6 bytes (=1 for opcode, 4 for sect addr, 1 for
> data). We are finalizing the patch for review.
>
> Since cadence qspi controller do support the 8-byte read/write in STIG
> mode, I have tried here to enable that in write_reg(), similar to
> read_reg().
>

Sounds good.

Reviewed-by: Vignesh R <[email protected]>

> [1]
> https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf
>
>>
>>>> Signed-off-by: Purna Chandra Mandal <[email protected]>
>>>
>>> Looks good for me:
>>> Reviewed-by: Tudor Ambarus <[email protected]>
>>>
>>> Vignesh, can we have your R-b or T-b tag?
>>>
>>> Cheers,
>>> ta
>>>
>>>> ---
>>>>
>>>> drivers/mtd/spi-nor/cadence-quadspi.c | 15 ++++++++++++---
>>>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>>>> index 04cedd3a2bf6..7f78f9409ddd 100644
>>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>>>> @@ -418,9 +418,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>>>> void __iomem *reg_base = cqspi->iobase;
>>>> unsigned int reg;
>>>> unsigned int data;
>>>> + u32 write_len;
>>>> int ret;
>>>>
>>>> - if (n_tx > 4 || (n_tx && !txbuf)) {
>>>> + if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
>>>> dev_err(nor->dev,
>>>> "Invalid input argument, cmdlen %d txbuf 0x%p\n",
>>>> n_tx, txbuf);
>>>> @@ -433,10 +434,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
>>>> reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
>>>> << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
>>>> data = 0;
>>>> - memcpy(&data, txbuf, n_tx);
>>>> + write_len = (n_tx > 4) ? 4 : n_tx;
>>>> + memcpy(&data, txbuf, write_len);
>>>> + txbuf += write_len;
>>>> writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
>>>> - }
>>>>
>>>> + if (n_tx > 4) {
>>>> + data = 0;
>>>> + write_len = n_tx - 4;
>>>> + memcpy(&data, txbuf, write_len);
>>>> + writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
>>>> + }
>>>> + }
>>>> ret = cqspi_exec_flash_cmd(cqspi, reg);
>>>> return ret;
>>>> }
>>>>
>>

--
Regards
Vignesh

2019-02-10 18:57:10

by Boris Brezillon

Subject: Re: mtd: spi-nor: cadence-quadspi: write upto 8-bytes data in STIG mode

From: Boris Brezillon <[email protected]>

On Mon, 2019-01-28 at 05:02:29 UTC, Purna Chandra Mandal wrote:
> cadence-quadspi controller allows upto eight bytes of data to
> be written in software Triggered Instruction generator (STIG) mode
> of operation. Lower 4 bytes are written through writedatalower and
> upper 4 bytes by writedataupper register.
>
> This patch allows all the 8 bytes to be written.
>
> Signed-off-by: Purna Chandra Mandal <[email protected]>
> Reviewed-by: Tudor Ambarus <[email protected]>
> Reviewed-by: Vignesh R <[email protected]>

Applied to http://git.infradead.org/linux-mtd.git spi-nor/next, thanks.

Boris