From: Gabriel Fernandez <[email protected]>
This patch-set fixes minor corrections (fixes and documentation alignment)
- add missing parent clocks
- don't change parent on set rate for kernel clocks
- set ck_csi clock as critical
- fix divider configuration
Gabriel Fernandez (7):
clk: stm32mp1: parent clocks update
clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
clk: stm32mp1: set ck_csi as critical clock
clk: stm32mp1: fix mcu divider table
clk: stm32mp1: fix HSI divider flag
clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
clk: stm32mp1: fix bit width of hse_rtc divider
drivers/clk/clk-stm32mp1.c | 36 +++++++++++++++++++-----------------
1 file changed, 19 insertions(+), 17 deletions(-)
--
2.17.0
From: Gabriel Fernandez <[email protected]>
The divider of HSI (clk-hsi-div) is power of two divider.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 385dac678a7f..863586a71d49 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1656,8 +1656,8 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
static const struct clock_config stm32mp1_clock_cfg[] = {
/* Oscillator divider */
- DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
- CLK_DIVIDER_READ_ONLY),
+ DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
+ RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
/* External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
--
2.17.0
From: Gabriel Fernandez <[email protected]>
ck_csi is used for IO compensation so it should be
considered as "always-on" and kept on.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index e72079de83f4..5b30e4eeca2c 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1661,7 +1661,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
/* External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
- GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
+ GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
+ RCC_OCENSETR, 4, 0),
GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
--
2.17.0
From: Gabriel Fernandez <[email protected]>
This patch fixes the bit width of the hse rtc divider.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6c99950c6135..fc75cf12f0e5 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1961,7 +1961,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
/* RTC clock */
- DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
+ DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_PARENT,
--
2.17.0
From: Gabriel Fernandez <[email protected]>
This patch updates parent clocks for axi, fdcan, sai and adc12.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce..be2ed35977ca 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
};
static const char * const axi_src[] = {
- "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+ "ck_hsi", "ck_hse", "pll2_p"
};
static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
};
static const char * const fdcan_src[] = {
- "ck_hse", "pll3_q", "pll4_q"
+ "ck_hse", "pll3_q", "pll4_q", "pll4_r"
};
static const char * const sai_src[] = {
- "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+ "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
};
static const char * const sai2_src[] = {
- "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+ "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
};
static const char * const adc12_src[] = {
- "pll4_q", "ck_per"
+ "pll4_r", "ck_per", "pll3_q"
};
static const char * const dsi_src[] = {
--
2.17.0
From: Gabriel Fernandez <[email protected]>
index 8: ck_mcuss divided by 256 (not 512)
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 5b30e4eeca2c..385dac678a7f 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -269,7 +269,7 @@ static const struct clk_div_table axi_div_table[] = {
static const struct clk_div_table mcu_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
{ 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
- { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
+ { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
{ 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
{ 0 },
};
--
2.17.0
From: Gabriel Fernandez <[email protected]>
Don't change parent during a set rate for Kernel clocks.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index be2ed35977ca..e72079de83f4 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct device *dev,
MGATE_MP1(_id, _name, _parent, _flags, _mgate)
#define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
- COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
- _MGATE_MP1(_mgate),\
- _MMUX(_mmux),\
- _NO_DIV)
+ COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
+ CLK_SET_RATE_NO_REPARENT | _flags,\
+ _MGATE_MP1(_mgate),\
+ _MMUX(_mmux),\
+ _NO_DIV)
enum {
G_SAI1,
@@ -1952,7 +1953,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
- COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
+ COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
+ CLK_SET_RATE_NO_REPARENT,
_NO_GATE,
_MMUX(M_ETHCK),
_DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
--
2.17.0
From: Gabriel Fernandez <[email protected]>
This patch removes unnecessary CLK_DIVIDER_ALLOW_ZERO flag of
ethptp_k and ck_hse_rtc clocks.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/clk-stm32mp1.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 863586a71d49..6c99950c6135 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1958,11 +1958,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
CLK_SET_RATE_NO_REPARENT,
_NO_GATE,
_MMUX(M_ETHCK),
- _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
+ _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
/* RTC clock */
- DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
- CLK_DIVIDER_ALLOW_ZERO),
+ DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0),
COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
CLK_SET_RATE_PARENT,
--
2.17.0
Quoting [email protected] (2019-02-12 05:51:50)
> From: Gabriel Fernandez <[email protected]>
>
> ck_csi is used for IO compensation so it should be
> considered as "always-on" and kept on.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
> drivers/clk/clk-stm32mp1.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
> index e72079de83f4..5b30e4eeca2c 100644
> --- a/drivers/clk/clk-stm32mp1.c
> +++ b/drivers/clk/clk-stm32mp1.c
> @@ -1661,7 +1661,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
>
> /* External / Internal Oscillators */
> GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
> - GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
> + GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
Please add a comment to the code indicating this so we know why critical
is here without reading git history.
Quoting [email protected] (2019-02-12 05:51:51)
> From: Gabriel Fernandez <[email protected]>
>
> index 8: ck_mcuss divided by 256 (not 512)
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
Any Fixes tag?
Quoting [email protected] (2019-02-12 05:51:52)
> From: Gabriel Fernandez <[email protected]>
>
> The divider of HSI (clk-hsi-div) is power of two divider.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
Any Fixes tag?
Quoting [email protected] (2019-02-12 05:51:54)
> From: Gabriel Fernandez <[email protected]>
>
> This patch fixes the bit width of the hse rtc divider.
Fixes tag?
Also, commit text shouldn't be written with "this patch". It should say
something more like "Fix the bit width of the hse rtc divider because
it's off by one".
Quoting [email protected] (2019-02-12 05:51:53)
> From: Gabriel Fernandez <[email protected]>
>
> This patch removes unnecessary CLK_DIVIDER_ALLOW_ZERO flag of
> ethptp_k and ck_hse_rtc clocks.
Why is it unnecessary? Please write the motivation in the commit text so
we can know why things are the way they are.
Quoting [email protected] (2019-02-12 05:51:48)
> From: Gabriel Fernandez <[email protected]>
>
> This patch updates parent clocks for axi, fdcan, sai and adc12.
Why?
Quoting [email protected] (2019-02-12 05:51:49)
> From: Gabriel Fernandez <[email protected]>
>
> Don't change parent during a set rate for Kernel clocks.
Why?