From: Wangyan Wang <[email protected]>
V4 adopt maintainer's suggestion.
Here is the change list between V4 & V5
1. add Reviewed-by:CK Hu <[email protected]>
in " drm/mediatek: fix the rate ..." commit message.
2. describe the reason why mt7623 clock of hdmi
is more stable than before.
the tvdpll should be stable in hdmi normal setting
to guarantee clock of hdmi stable, but the tvdpll
may be changed in original code ,the patch is to
deal with the problem, you can find more descriptions
in patch "drm/mediatek:using different flags of clk ...".
chunhui dai (8):
drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
hardware
drm/mediatek: move the setting of fixed divider
drm/mediatek: using different flags of clk for HDMI phy
drm/mediatek: fix the rate and divder of hdmi phy for MT2701
clk: mediatek: add MUX_GATE_FLAGS_2
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
drm/mediatek: using new factor for tvdpll in MT2701
drm/mediatek: fix the rate of parent for hdmi phy in MT2701
drivers/clk/mediatek/clk-mt2701.c | 4 +-
drivers/clk/mediatek/clk-mtk.c | 2 +-
drivers/clk/mediatek/clk-mtk.h | 20 ++++++---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++
8 files changed, 102 insertions(+), 52 deletions(-)
--
2.14.1
From: chunhui dai <[email protected]>
Due to a clerical error,there is one zero less for 12800000.
Fix it for 128000000.
Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
Reviewed-by: CK Hu <[email protected]>
Signed-off-by: chunhui dai <[email protected]>
Signed-off-by: wangyan wang <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
index 43bc058d5528..88dd9e812ca0 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
@@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
if (rate <= 64000000)
pos_div = 3;
- else if (rate <= 12800000)
- pos_div = 1;
+ else if (rate <= 128000000)
+ pos_div = 2;
else
pos_div = 1;
--
2.14.1
From: chunhui dai <[email protected]>
The factor depends on the divider of DPI in MT2701, therefore,
we should fix this factor to the right and new one.
Signed-off-by: chunhui dai <[email protected]>
Signed-off-by: wangyan wang <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 69c6e42dad6b..4a2f4a650494 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -662,13 +662,11 @@ static unsigned int mt8173_calculate_factor(int clock)
static unsigned int mt2701_calculate_factor(int clock)
{
if (clock <= 64000)
- return 16;
- else if (clock <= 128000)
- return 8;
- else if (clock <= 256000)
return 4;
- else
+ else if (clock <= 128000)
return 2;
+ else
+ return 1;
}
static const struct mtk_dpi_conf mt8173_conf = {
--
2.14.1
From: chunhui dai <[email protected]>
The MUX clock of dpi1_sel should select the closet clock for itself.
We could add this flag to enable this function of MUX in CCF.
Signed-off-by: chunhui dai <[email protected]>
Signed-off-by: wangyan wang <[email protected]>
---
drivers/clk/mediatek/clk-mt2701.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index ab6ab07f53e6..905a2316f6a7 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = {
0x0080, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x0080, 16, 3, 23),
- MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
- 0x0080, 24, 2, 31),
+ MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
+ 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0x0090, 0, 3, 7),
--
2.14.1
On Wed, 2019-02-20 at 10:53 +0800, wangyan wang wrote:
> From: Wangyan Wang <[email protected]>
>
> V4 adopt maintainer's suggestion.
> Here is the change list between V4 & V5
> 1. add Reviewed-by:CK Hu <[email protected]>
> in " drm/mediatek: fix the rate ..." commit message.
>
> 2. describe the reason why mt7623 clock of hdmi
> is more stable than before.
> the tvdpll should be stable in hdmi normal setting
> to guarantee clock of hdmi stable, but the tvdpll
> may be changed in original code ,the patch is to
> deal with the problem, you can find more descriptions
> in patch "drm/mediatek:using different flags of clk ...".
>
>
> chunhui dai (8):
> drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
> hardware
> drm/mediatek: move the setting of fixed divider
> drm/mediatek: using different flags of clk for HDMI phy
> drm/mediatek: fix the rate and divder of hdmi phy for MT2701
> clk: mediatek: add MUX_GATE_FLAGS_2
> clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
> drm/mediatek: using new factor for tvdpll in MT2701
> drm/mediatek: fix the rate of parent for hdmi phy in MT2701
>
> drivers/clk/mediatek/clk-mt2701.c | 4 +-
> drivers/clk/mediatek/clk-mtk.c | 2 +-
> drivers/clk/mediatek/clk-mtk.h | 20 ++++++---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +---
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++---
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++
> 8 files changed, 102 insertions(+), 52 deletions(-)
>
I could see the Debian Gnome desktop on my MT7623 R2.
Tested-by: Ryder Lee <[email protected]>