This series adds support for the "hardware message box" in sun8i, sun9i,
and sun50i SoCs, used for communication with the ARISC management
processor (the platform's equivalent of the ARM SCP). The end goal is to
use the arm_scpi driver as a client, communicating with firmware running
on the ARISC CPU, or to use the mailbox to forward NMIs that the
firmware picks up from R_INTC.
Changes from v1:
- Marked message box clocks as critical instead of hacks in the driver
- 8 unidirectional channels instead of 4 bidirectional pairs
- Use per-SoC compatible strings and an A31 fallback compatible
- Dropped the mailbox framework patch
- Include DT patches for SoCs that document the message box
Samuel Holland (10):
clk: sunxi-ng: sun8i: Mark the msgbox clock as critical
clk: sunxi-ng: sun9i: Mark the msgbox clock as critical
clk: sunxi-ng: sun50i: Mark the msgbox clock as critical
dt-bindings: mailbox: Add a sunxi message box binding
mailbox: sunxi-msgbox: Add a new mailbox driver
ARM: dts: sunxi: a80: Add msgbox node
ARM: dts: sunxi: a83t: Add msgbox node
ARM: dts: sunxi: h3/h5: Add msgbox node
arm64: dts: allwinner: a64: Add msgbox node
arm64: dts: allwinner: h6: Add msgbox node
.../bindings/mailbox/sunxi-msgbox.txt | 44 +++
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +
arch/arm/boot/dts/sun9i-a80.dtsi | 10 +
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
drivers/mailbox/Kconfig | 11 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/sunxi-msgbox.c | 315 ++++++++++++++++++
16 files changed, 429 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
create mode 100644 drivers/mailbox/sunxi-msgbox.c
--
2.19.2
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the message box to forward requests to power management firmware
running on a separate CPU.
It is not enough for the secure monitor to enable the clock each time
Linux performs a SMC into EL3, as both the firmware and Linux can run
concurrently on separate CPUs. So it is never safe for Linux to turn
this clock off, and it should be marked as critical.
At this time, such power management firmware only exists for the H5.
However, it makes sense to take care of all CCU drivers now for
consistency, and to ease the transition in the future, once firmware is
ported to the other SoCs.
Signed-off-by: Samuel Holland <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index a4fa2945f230..22d09cb20326 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -263,7 +263,7 @@ static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x064, BIT(21), 0);
+ 0x064, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index c7bf814dfd2b..6d25b7a1c81e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -275,7 +275,7 @@ static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x064, BIT(21), 0);
+ 0x064, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 2d6555d73170..85809c454b1f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -347,7 +347,7 @@ static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x064, BIT(21), 0);
+ 0x064, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index e71e2451c2e3..d09629688fd4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -281,7 +281,7 @@ static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x064, BIT(21), 0);
+ 0x064, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
--
2.19.2
The H6 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d93a7add67e7..950681b2f7d9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -189,6 +189,16 @@
#interrupt-cells = <3>;
};
+ msgbox: mailbox@3003000 {
+ compatible = "allwinner,sun50i-h6-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x03003000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
--
2.19.2
Allwinner sun8i, sun9i, and sun50i SoCs contain a hardware message box
used for communication between the ARM CPUs and the ARISC management
coprocessor. The hardware contains 8 unidirectional 4-message FIFOs.
Add a driver for it, so it can be used for SCPI or other communication
protocols.
Signed-off-by: Samuel Holland <[email protected]>
---
drivers/mailbox/Kconfig | 11 ++
drivers/mailbox/Makefile | 2 +
drivers/mailbox/sunxi-msgbox.c | 315 +++++++++++++++++++++++++++++++++
3 files changed, 328 insertions(+)
create mode 100644 drivers/mailbox/sunxi-msgbox.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e93e98..6309e755d04a 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,15 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config SUNXI_MSGBOX
+ tristate "Allwinner sunxi Message Box"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ default ARCH_SUNXI
+ help
+ Mailbox implementation for the hardware message box present in
+ Allwinner sun8i, sun9i, and sun50i SoCs. The hardware message box is
+ used for communication between the application CPUs and the power
+ management coprocessor.
+
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d011ae..f29a119a3fac 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_SUNXI_MSGBOX) += sunxi-msgbox.o
diff --git a/drivers/mailbox/sunxi-msgbox.c b/drivers/mailbox/sunxi-msgbox.c
new file mode 100644
index 000000000000..fb0d733dd3b4
--- /dev/null
+++ b/drivers/mailbox/sunxi-msgbox.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2017-2019 Samuel Holland <[email protected]>
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+#define NUM_CHANS 8
+
+#define CTRL_REG(n) (0x0000 + 0x4 * ((n) / 4))
+#define CTRL_RX(n) BIT(0 + 8 * ((n) % 4))
+#define CTRL_TX(n) BIT(4 + 8 * ((n) % 4))
+
+#define REMOTE_IRQ_EN_REG 0x0040
+#define REMOTE_IRQ_STATUS_REG 0x0050
+#define LOCAL_IRQ_EN_REG 0x0060
+#define LOCAL_IRQ_STATUS_REG 0x0070
+
+#define RX_IRQ(n) BIT(0 + 2 * (n))
+#define RX_IRQ_MASK 0x5555
+#define TX_IRQ(n) BIT(1 + 2 * (n))
+#define TX_IRQ_MASK 0xaaaa
+
+#define FIFO_STATUS_REG(n) (0x0100 + 0x4 * (n))
+#define FIFO_STATUS_MASK BIT(0)
+
+#define MSG_STATUS_REG(n) (0x0140 + 0x4 * (n))
+#define MSG_STATUS_MASK GENMASK(2, 0)
+
+#define MSG_DATA_REG(n) (0x0180 + 0x4 * (n))
+
+#define mbox_dbg(mbox, ...) dev_dbg((mbox)->controller.dev, __VA_ARGS__)
+
+struct sunxi_msgbox {
+ struct mbox_controller controller;
+ struct clk *clk;
+ spinlock_t lock;
+ void __iomem *regs;
+};
+
+static bool sunxi_msgbox_last_tx_done(struct mbox_chan *chan);
+static bool sunxi_msgbox_peek_data(struct mbox_chan *chan);
+
+static inline int channel_number(struct mbox_chan *chan)
+{
+ return chan - chan->mbox->chans;
+}
+
+static inline struct sunxi_msgbox *channel_to_msgbox(struct mbox_chan *chan)
+{
+ return (struct sunxi_msgbox *)chan->con_priv;
+}
+
+static irqreturn_t sunxi_msgbox_irq(int irq, void *dev_id)
+{
+ struct mbox_chan *chan;
+ struct sunxi_msgbox *mbox = dev_id;
+ int n;
+ uint32_t msg, status;
+
+ status = readl(mbox->regs + LOCAL_IRQ_STATUS_REG);
+ if (!(status & RX_IRQ_MASK))
+ return IRQ_NONE;
+
+ for (n = 0; n < NUM_CHANS; ++n) {
+ if (!(status & RX_IRQ(n)))
+ continue;
+ chan = &mbox->controller.chans[n];
+ while (sunxi_msgbox_peek_data(chan)) {
+ msg = readl(mbox->regs + MSG_DATA_REG(n));
+ mbox_dbg(mbox, "Channel %d received 0x%08x\n", n, msg);
+ mbox_chan_received_data(chan, &msg);
+ }
+ /* The IRQ can be cleared only when the FIFO is empty. */
+ writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STATUS_REG);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int sunxi_msgbox_send_data(struct mbox_chan *chan, void *data)
+{
+ struct sunxi_msgbox *mbox = channel_to_msgbox(chan);
+ int n = channel_number(chan);
+ uint32_t msg = *(uint32_t *)data;
+
+ /* Using a channel backwards gets the hardware into a bad state. */
+ if (WARN_ON_ONCE(!(readl(mbox->regs + CTRL_REG(n)) & CTRL_TX(n))))
+ return 0;
+
+ /* We cannot post a new message if the FIFO is full. */
+ if (readl(mbox->regs + FIFO_STATUS_REG(n)) & FIFO_STATUS_MASK) {
+ mbox_dbg(mbox, "Channel %d busy sending 0x%08x\n", n, msg);
+ return -EBUSY;
+ }
+
+ writel(msg, mbox->regs + MSG_DATA_REG(n));
+ mbox_dbg(mbox, "Channel %d sent 0x%08x\n", n, msg);
+
+ return 0;
+}
+
+static int sunxi_msgbox_startup(struct mbox_chan *chan)
+{
+ struct sunxi_msgbox *mbox = channel_to_msgbox(chan);
+ int n = channel_number(chan);
+
+ /* The coprocessor is responsible for setting channel directions. */
+ if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
+ /* Clear existing messages in the receive FIFO. */
+ while (sunxi_msgbox_peek_data(chan))
+ readl(mbox->regs + MSG_DATA_REG(n));
+ writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STATUS_REG);
+
+ /* Enable the receive interrupt. */
+ spin_lock(&mbox->lock);
+ writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) | RX_IRQ(n),
+ mbox->regs + LOCAL_IRQ_EN_REG);
+ spin_unlock(&mbox->lock);
+ }
+
+ mbox_dbg(mbox, "Channel %d startup\n", n);
+
+ return 0;
+}
+
+static void sunxi_msgbox_shutdown(struct mbox_chan *chan)
+{
+ struct sunxi_msgbox *mbox = channel_to_msgbox(chan);
+ int n = channel_number(chan);
+
+ if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
+ /* Disable the receive interrupt. */
+ spin_lock(&mbox->lock);
+ writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) & ~RX_IRQ(n),
+ mbox->regs + LOCAL_IRQ_EN_REG);
+ spin_unlock(&mbox->lock);
+
+ /* Clear existing messages in the receive FIFO. */
+ while (sunxi_msgbox_peek_data(chan))
+ readl(mbox->regs + MSG_DATA_REG(n));
+ writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STATUS_REG);
+ }
+
+ mbox_dbg(mbox, "Channel %d shutdown\n", n);
+}
+
+static bool sunxi_msgbox_last_tx_done(struct mbox_chan *chan)
+{
+ struct sunxi_msgbox *mbox = channel_to_msgbox(chan);
+ int n = channel_number(chan);
+
+ /*
+ * The hardware allows snooping on the remote user's IRQ status. We
+ * consider a message to be acknowledged only when the receive IRQ for
+ * that channel is cleared. As the hardware only allows clearing the
+ * IRQ for a channel when the FIFO is empty, this still ensures that
+ * the message has actually been read. It also gives the receiver an
+ * opportunity to perform minimal processing before acknowledging a
+ * message.
+ */
+ return !(readl(mbox->regs + REMOTE_IRQ_STATUS_REG) & RX_IRQ(n));
+}
+
+static bool sunxi_msgbox_peek_data(struct mbox_chan *chan)
+{
+ struct sunxi_msgbox *mbox = channel_to_msgbox(chan);
+ int n = channel_number(chan);
+
+ return (readl(mbox->regs + MSG_STATUS_REG(n)) & MSG_STATUS_MASK) > 0;
+}
+
+static const struct mbox_chan_ops sunxi_msgbox_chan_ops = {
+ .send_data = sunxi_msgbox_send_data,
+ .startup = sunxi_msgbox_startup,
+ .shutdown = sunxi_msgbox_shutdown,
+ .last_tx_done = sunxi_msgbox_last_tx_done,
+ .peek_data = sunxi_msgbox_peek_data,
+};
+
+static int sunxi_msgbox_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mbox_chan *chans;
+ struct reset_control *reset;
+ struct resource *res;
+ struct sunxi_msgbox *mbox;
+ int i, ret;
+
+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
+ if (!mbox)
+ return -ENOMEM;
+
+ chans = devm_kcalloc(dev, NUM_CHANS, sizeof(*chans), GFP_KERNEL);
+ if (!chans)
+ return -ENOMEM;
+
+ for (i = 0; i < NUM_CHANS; ++i)
+ chans[i].con_priv = mbox;
+
+ mbox->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(mbox->clk)) {
+ ret = PTR_ERR(mbox->clk);
+ dev_err(dev, "Failed to get clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(mbox->clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable clock: %d\n", ret);
+ return ret;
+ }
+
+ reset = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(reset)) {
+ ret = PTR_ERR(reset);
+ dev_err(dev, "Failed to get reset control: %d\n", ret);
+ goto err_disable_unprepare;
+ }
+
+ ret = reset_control_deassert(reset);
+ if (ret) {
+ dev_err(dev, "Failed to deassert reset: %d\n", ret);
+ goto err_disable_unprepare;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ ret = -ENODEV;
+ goto err_disable_unprepare;
+ }
+
+ mbox->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mbox->regs)) {
+ ret = PTR_ERR(mbox->regs);
+ dev_err(dev, "Failed to map MMIO resource: %d\n", ret);
+ goto err_disable_unprepare;
+ }
+
+ /* Disable all interrupts for this end of the msgbox. */
+ writel(0, mbox->regs + LOCAL_IRQ_EN_REG);
+
+ ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0),
+ sunxi_msgbox_irq, 0, dev_name(dev), mbox);
+ if (ret) {
+ dev_err(dev, "Failed to register IRQ handler: %d\n", ret);
+ goto err_disable_unprepare;
+ }
+
+ mbox->controller.dev = dev;
+ mbox->controller.ops = &sunxi_msgbox_chan_ops;
+ mbox->controller.chans = chans;
+ mbox->controller.num_chans = NUM_CHANS;
+ mbox->controller.txdone_irq = false;
+ mbox->controller.txdone_poll = true;
+ mbox->controller.txpoll_period = 5;
+
+ spin_lock_init(&mbox->lock);
+ platform_set_drvdata(pdev, mbox);
+
+ ret = mbox_controller_register(&mbox->controller);
+ if (ret) {
+ dev_err(dev, "Failed to register controller: %d\n", ret);
+ goto err_disable_unprepare;
+ }
+
+ return 0;
+
+err_disable_unprepare:
+ clk_disable_unprepare(mbox->clk);
+
+ return ret;
+}
+
+static int sunxi_msgbox_remove(struct platform_device *pdev)
+{
+ struct sunxi_msgbox *mbox = platform_get_drvdata(pdev);
+
+ mbox_controller_unregister(&mbox->controller);
+ clk_disable_unprepare(mbox->clk);
+
+ return 0;
+}
+
+static const struct of_device_id sunxi_msgbox_of_match[] = {
+ { .compatible = "allwinner,sun6i-a31-msgbox", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sunxi_msgbox_of_match);
+
+static struct platform_driver sunxi_msgbox_driver = {
+ .driver = {
+ .name = "sunxi-msgbox",
+ .of_match_table = sunxi_msgbox_of_match,
+ },
+ .probe = sunxi_msgbox_probe,
+ .remove = sunxi_msgbox_remove,
+};
+module_platform_driver(sunxi_msgbox_driver);
+
+MODULE_AUTHOR("Samuel Holland <[email protected]>");
+MODULE_DESCRIPTION("Allwinner sunxi Message Box");
+MODULE_LICENSE("GPL v2");
--
2.19.2
The A64 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 2abb335145a6..29ee8f0f833a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -447,6 +447,16 @@
reg = <0x1c14000 0x400>;
};
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun50i-a64-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
--
2.19.2
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the message box to forward requests to power management firmware
running on a separate CPU.
It is not enough for the secure monitor to enable the clock each time
Linux performs a SMC into EL3, as both the firmware and Linux can run
concurrently on separate CPUs. So it is never safe for Linux to turn
this clock off, and it should be marked as critical.
At this time, such power management firmware does not exist for the A80.
However, it makes sense to take care of all CCU drivers now for
consistency, and to ease the transition in the future, once firmware is
ported to this SoC.
Signed-off-by: Samuel Holland <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index 8936ef87652c..f9309782e7d8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -756,7 +756,7 @@ static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
0x584, BIT(17), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x584, BIT(21), 0);
+ 0x584, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x584, BIT(22), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
--
2.19.2
The A80 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d9532fb1ef65..10e878f94fc0 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -283,6 +283,16 @@
};
};
+ msgbox: mailbox@803000 {
+ compatible = "allwinner,sun9i-a80-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x00803000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
ehci0: usb@a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
--
2.19.2
The A83T SoC contains a message box that can be used to send messages
and interrupts back and forth between the ARM application CPUs and the
ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index b099d2fbb5cd..c80c4f942439 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -546,6 +546,16 @@
reg = <0x1c14000 0x400>;
};
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-a83t-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a83t-musb",
"allwinner,sun8i-a33-musb";
--
2.19.2
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the message box to forward requests to power management firmware
running on a separate CPU.
It is not enough for the secure monitor to enable the clock each time
Linux performs a SMC into EL3, as both the firmware and Linux can run
concurrently on separate CPUs. So it is never safe for Linux to turn
this clock off, and it should be marked as critical.
At this time, such power management firmware only exists for the A64.
However, it makes sense to take care of all CCU drivers now for
consistency, and to ease the transition in the future, once firmware is
ported to the other SoCs.
Signed-off-by: Samuel Holland <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 932836d26e2b..7780e855c56f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -350,7 +350,7 @@ static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
- 0x064, BIT(21), 0);
+ 0x064, BIT(21), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 139e8389615c..a7fee407a1c8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -340,7 +340,7 @@ static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0x70c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
- 0x71c, BIT(0), 0);
+ 0x71c, BIT(0), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
0x72c, BIT(0), 0);
--
2.19.2
This mailbox hardware is present in Allwinner sun8i, sun9i, and sun50i
SoCs. Add a device tree binding for it.
Signed-off-by: Samuel Holland <[email protected]>
---
.../bindings/mailbox/sunxi-msgbox.txt | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt b/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
new file mode 100644
index 000000000000..4560ab8efeca
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
@@ -0,0 +1,44 @@
+Allwinner sun6i Message Box
+===========================
+
+The hardware message box on sun6i and newer sunxi SoCs is a two-user mailbox
+controller containing 8 unidirectional FIFOs. An interrupt is raised for
+received messages, but software must poll to know when a transmitted message has
+been acknowledged by the remote user.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Mailbox Device Node:
+====================
+
+Required properties:
+--------------------
+- compatible: Must contain at least "allwinner,sun6i-a31-msgbox".
+ Should also contain another SoC-specific string when
+ used on other SoCs which are compatible, e.g.
+ - allwinner,sun6i-a31-msgbox
+ - allwinner,sun8i-a83t-msgbox, allwinner,sun6i-a31-msgbox
+ - allwinner,sun8i-h3-msgbox, allwinner,sun6i-a31-msgbox
+ - allwinner,sun9i-a80-msgbox, allwinner,sun6i-a31-msgbox
+ - allwinner,sun50i-a64-msgbox, allwinner,sun6i-a31-msgbox
+ - allwinner,sun50i-h6-msgbox, allwinner,sun6i-a31-msgbox
+- reg: Contains the mailbox register address range (base
+ address and length).
+- clocks: phandle for the bus clock controller and specifier.
+- resets: phandle for the bus reset controller and specifier.
+- interrupts: Contains interrupt information for the mailbox.
+- #mbox-cells: Must be 1.
+
+Example:
+--------
+
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-h3-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
--
2.19.2
The H3 and H5 SoCs contain a message box that can be used to send
messages and interrupts back and forth between the ARM application CPUs
and the ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland <[email protected]>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index a4c757c0b741..a42fd3f9739e 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -227,6 +227,16 @@
#size-cells = <0>;
};
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-h3-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x400>;
--
2.19.2
On Thu, Feb 28, 2019 at 11:29:37PM -0600, Samuel Holland wrote:
> This series adds support for the "hardware message box" in sun8i, sun9i,
> and sun50i SoCs, used for communication with the ARISC management
> processor (the platform's equivalent of the ARM SCP). The end goal is to
> use the arm_scpi driver as a client, communicating with firmware running
> on the ARISC CPU, or to use the mailbox to forward NMIs that the
> firmware picks up from R_INTC.
>
> Changes from v1:
> - Marked message box clocks as critical instead of hacks in the driver
> - 8 unidirectional channels instead of 4 bidirectional pairs
> - Use per-SoC compatible strings and an A31 fallback compatible
> - Dropped the mailbox framework patch
> - Include DT patches for SoCs that document the message box
>
> Samuel Holland (10):
> clk: sunxi-ng: sun8i: Mark the msgbox clock as critical
> clk: sunxi-ng: sun9i: Mark the msgbox clock as critical
> clk: sunxi-ng: sun50i: Mark the msgbox clock as critical
> dt-bindings: mailbox: Add a sunxi message box binding
> mailbox: sunxi-msgbox: Add a new mailbox driver
> ARM: dts: sunxi: a80: Add msgbox node
> ARM: dts: sunxi: a83t: Add msgbox node
> ARM: dts: sunxi: h3/h5: Add msgbox node
> arm64: dts: allwinner: a64: Add msgbox node
> arm64: dts: allwinner: h6: Add msgbox node
>
> .../bindings/mailbox/sunxi-msgbox.txt | 44 +++
> arch/arm/boot/dts/sun8i-a83t.dtsi | 10 +
> arch/arm/boot/dts/sun9i-a80.dtsi | 10 +
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 +
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 +
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 2 +-
> drivers/mailbox/Kconfig | 11 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/sunxi-msgbox.c | 315 ++++++++++++++++++
> 16 files changed, 429 insertions(+), 7 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
> create mode 100644 drivers/mailbox/sunxi-msgbox.c
Hello
Appart from applying/compiling/booting, does it exists some way to test it ? check it works ?
Regards
Hi
On Thu, Feb 28, 2019 at 11:29:37PM -0600, Samuel Holland wrote:
> This series adds support for the "hardware message box" in sun8i, sun9i,
> and sun50i SoCs, used for communication with the ARISC management
> processor (the platform's equivalent of the ARM SCP). The end goal is to
> use the arm_scpi driver as a client, communicating with firmware running
> on the ARISC CPU, or to use the mailbox to forward NMIs that the
> firmware picks up from R_INTC.
>
> Changes from v1:
> - Marked message box clocks as critical instead of hacks in the driver
> - 8 unidirectional channels instead of 4 bidirectional pairs
> - Use per-SoC compatible strings and an A31 fallback compatible
> - Dropped the mailbox framework patch
> - Include DT patches for SoCs that document the message box
>
> Samuel Holland (10):
> clk: sunxi-ng: sun8i: Mark the msgbox clock as critical
> clk: sunxi-ng: sun9i: Mark the msgbox clock as critical
> clk: sunxi-ng: sun50i: Mark the msgbox clock as critical
> dt-bindings: mailbox: Add a sunxi message box binding
> mailbox: sunxi-msgbox: Add a new mailbox driver
> ARM: dts: sunxi: a80: Add msgbox node
> ARM: dts: sunxi: a83t: Add msgbox node
> ARM: dts: sunxi: h3/h5: Add msgbox node
> arm64: dts: allwinner: a64: Add msgbox node
> arm64: dts: allwinner: h6: Add msgbox node
It looks good to me but a few things:
- There's no reason to split the first three patches, so they should
all be merged
- You might consider using a YAML schemas for your DT bindings
documentation. That will bring a more formal descriptiion and DT
validation.
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Quoting Samuel Holland (2019-02-28 21:29:40)
> The msgbox clock is critical because the hardware is shared between
> Linux and system firmware. The message box may be used by the EL3 secure
> monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
> ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
> uses the message box to forward requests to power management firmware
> running on a separate CPU.
>
> It is not enough for the secure monitor to enable the clock each time
> Linux performs a SMC into EL3, as both the firmware and Linux can run
> concurrently on separate CPUs. So it is never safe for Linux to turn
> this clock off, and it should be marked as critical.
>
> At this time, such power management firmware only exists for the A64.
> However, it makes sense to take care of all CCU drivers now for
> consistency, and to ease the transition in the future, once firmware is
> ported to the other SoCs.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
> drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index 932836d26e2b..7780e855c56f 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -350,7 +350,7 @@ static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
> static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
> 0x064, BIT(20), 0);
> static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
> - 0x064, BIT(21), 0);
> + 0x064, BIT(21), CLK_IS_CRITICAL);
Please add a comment explaining why CLK_IS_CRITICAL is used. It helps us
remember years from now without having to dig in the git history.