From: Thor Thayer <[email protected]>
Reserve ECC Double Bit Error SMC call to alert U-Boot that
a DBE has occurred. Moving the call from local EDAC header
file to this common file.
Reviewed-by: Richard Gong <[email protected]>
Reviewed-by: Alan Tull <[email protected]>
Signed-off-by: Thor Thayer <[email protected]>
---
include/linux/firmware/intel/stratix10-smc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h
index 5be5dab50b13..01684d935580 100644
--- a/include/linux/firmware/intel/stratix10-smc.h
+++ b/include/linux/firmware/intel/stratix10-smc.h
@@ -309,4 +309,23 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
#define INTEL_SIP_SMC_RSU_UPDATE \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
+
+/*
+ * Request INTEL_SIP_SMC_ECC_DBE
+ *
+ * Sync call used by service driver at EL1 to alert EL3 that a Double
+ * Bit ECC error has occurred.
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_ECC_DBE
+ * a1 SysManager Double Bit Error value
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
+#define INTEL_SIP_SMC_ECC_DBE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
+
#endif
--
2.7.4
From: Thor Thayer <[email protected]>
Use the global Stratix10 SMC defines instead of the local
S10 SMC defines.
Reviewed-by: Richard Gong <[email protected]>
Signed-off-by: Thor Thayer <[email protected]>
---
drivers/edac/altera_edac.c | 1 +
drivers/edac/altera_edac.h | 83 ----------------------------------------------
2 files changed, 1 insertion(+), 83 deletions(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 761199175c76..8816f74a22b4 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -9,6 +9,7 @@
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/edac.h>
+#include <linux/firmware/intel/stratix10-smc.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 1532ec9c3510..55654cc4bcdf 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -372,87 +372,4 @@ struct altr_arria10_edac {
struct notifier_block panic_notifier;
};
-/*
- * Functions specified by ARM SMC Calling convention:
- *
- * FAST call executes atomic operations, returns when the requested operation
- * has completed.
- * STD call starts a operation which can be preempted by a non-secure
- * interrupt. The call can return before the requested operation has
- * completed.
- *
- * a0..a7 is used as register names in the descriptions below, on arm32
- * that translates to r0..r7 and on arm64 to w0..w7.
- */
-
-#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
- ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
- ARM_SMCCC_OWNER_SIP, (func_num))
-
-#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
- ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
- ARM_SMCCC_OWNER_SIP, (func_num))
-
-#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
-#define INTEL_SIP_SMC_STATUS_OK 0x0
-#define INTEL_SIP_SMC_REG_ERROR 0x5
-
-/*
- * Request INTEL_SIP_SMC_REG_READ
- *
- * Read a protected register using SMCCC
- *
- * Call register usage:
- * a0: INTEL_SIP_SMC_REG_READ.
- * a1: register address.
- * a2-7: not used.
- *
- * Return status:
- * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
- * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
- * a1: Value in the register
- * a2-3: not used.
- */
-#define INTEL_SIP_SMC_FUNCID_REG_READ 7
-#define INTEL_SIP_SMC_REG_READ \
- INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
-
-/*
- * Request INTEL_SIP_SMC_REG_WRITE
- *
- * Write a protected register using SMCCC
- *
- * Call register usage:
- * a0: INTEL_SIP_SMC_REG_WRITE.
- * a1: register address
- * a2: value to program into register.
- * a3-7: not used.
- *
- * Return status:
- * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
- * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
- * a1-3: not used.
- */
-#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
-#define INTEL_SIP_SMC_REG_WRITE \
- INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
-
-/*
- * Request INTEL_SIP_SMC_ECC_DBE
- *
- * Sync call used by service driver at EL1 alert EL3 that a Double Bit
- * ECC error has occurred.
- *
- * Call register usage:
- * a0 INTEL_SIP_SMC_ECC_DBE
- * a1 SysManager Double Bit Error value
- * a2-7 not used
- *
- * Return status
- * a0 INTEL_SIP_SMC_STATUS_OK
- */
-#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
-#define INTEL_SIP_SMC_ECC_DBE \
- INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
-
#endif /* #ifndef _ALTERA_EDAC_H */
--
2.7.4
On Fri, Mar 29, 2019 at 09:43:58AM -0500, [email protected] wrote:
> From: Thor Thayer <[email protected]>
>
> Reserve ECC Double Bit Error SMC call to alert U-Boot that
> a DBE has occurred. Moving the call from local EDAC header
> file to this common file.
Is there any particular reason this needs to be two patches or can I
merge them into one?
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
On 4/2/19 3:55 AM, Borislav Petkov wrote:
> On Fri, Mar 29, 2019 at 09:43:58AM -0500, [email protected] wrote:
>> From: Thor Thayer <[email protected]>
>>
>> Reserve ECC Double Bit Error SMC call to alert U-Boot that
>> a DBE has occurred. Moving the call from local EDAC header
>> file to this common file.
>
> Is there any particular reason this needs to be two patches or can I
> merge them into one?
>
Yes, they can be merged into one. I split into 2 patches since the 1st
required the firmware directory sign-off and the 2nd required your EDAC
sign-off. I see your point, it could have been 1 patch.
Thanks for reviewing,
Thor
On Tue, Apr 02, 2019 at 08:34:18AM -0500, Thor Thayer wrote:
> Yes, they can be merged into one. I split into 2 patches since the 1st
> required the firmware directory sign-off and the 2nd required your EDAC
> sign-off. I see your point, it could have been 1 patch.
Ok, merged and applied.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.