The ARM PMU and ARM architected timer nodes are part of ARM CPU design
therefore they should not be inside the soc node. This also fixes DTC
W=1 warnings like:
arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5:
Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos3250.dtsi | 12 +++++-----
arch/arm/boot/dts/exynos4.dtsi | 12 +++++-----
arch/arm/boot/dts/exynos5250.dtsi | 40 +++++++++++++++----------------
arch/arm/boot/dts/exynos54xx.dtsi | 38 ++++++++++++++---------------
4 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 5892a9f7622f..af54b306204b 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -97,6 +97,12 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -673,12 +679,6 @@
status = "disabled";
};
- pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- };
-
ppmu_dmc0: ppmu_dmc0@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 6085e92ac2d7..1c21627e3c3c 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -51,6 +51,12 @@
serial3 = &serial_3;
};
+ pmu: pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <2 2>, <3 2>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -169,12 +175,6 @@
reg = <0x10440000 0x1000>;
};
- pmu: pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <2 2>, <3 2>;
- };
-
sys_reg: syscon@10010000 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 80986b97dfe5..96ace6a5e2f9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -157,6 +157,26 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <1 2>, <22 4>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ /*
+ * Unfortunately we need this since some versions
+ * of U-Boot on Exynos don't set the CNTFRQ register,
+ * so we need the value from DT.
+ */
+ clock-frequency = <24000000>;
+ };
+
soc: soc {
sysram@2020000 {
compatible = "mmio-sram";
@@ -227,20 +247,6 @@
power-domains = <&pd_mau>;
};
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- /*
- * Unfortunately we need this since some versions
- * of U-Boot on Exynos don't set the CNTFRQ register,
- * so we need the value from DT.
- */
- clock-frequency = <24000000>;
- };
-
mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
@@ -265,12 +271,6 @@
};
};
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <1 2>, <22 4>;
- };
-
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index de26e5ee0d2d..ae866bcc30c4 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -25,27 +25,27 @@
usbdrdphy1 = &usbdrd_phy1;
};
- soc: soc {
- arm_a7_pmu: arm-a7-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ arm_a7_pmu: arm-a7-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
- arm_a15_pmu: arm-a15-pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <1 2>,
- <7 0>,
- <16 6>,
- <19 2>;
- status = "disabled";
- };
+ arm_a15_pmu: arm-a15-pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <1 2>,
+ <7 0>,
+ <16 6>,
+ <19 2>;
+ status = "disabled";
+ };
+ soc: soc {
sysram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
--
2.17.1
The three fixed-clocks (xusbxti, xxti and xtcxo) are inputs to the
Exynos3250 therefore they should not be inside the soc node. This also
fixes DTC W=1 warning:
arch/arm/boot/dts/exynos3250.dtsi:112.21-139.5:
Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos3250.dtsi | 58 +++++++++++++++----------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 6e74e6815b01..8ce3a7786b19 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -97,6 +97,35 @@
};
};
+ fixed-rate-clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xusbxti: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xusbxti";
+ };
+
+ xxti: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xxti";
+ };
+
+ xtcxo: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xtcxo";
+ };
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,35 +138,6 @@
#size-cells = <1>;
ranges;
- fixed-rate-clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- xusbxti: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xusbxti";
- };
-
- xxti: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xxti";
- };
-
- xtcxo: clock@2 {
- compatible = "fixed-clock";
- reg = <2>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xtcxo";
- };
- };
-
sysram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
2.17.1
The Universal C210 (Exynos4210) uses the secure interface of MDMA0,
instead of regular one - non-secure MDMA1. DTS was overriding MDMA1
node address which caused DTC W=1 warning:
arch/arm/boot/dts/exynos4.dtsi:707.25-716.6:
Warning (simple_bus_reg): /soc/amba/mdma@12850000: simple-bus unit address format error, expected "12840000"
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos4.dtsi | 2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1c21627e3c3c..36ccf227434d 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -675,7 +675,7 @@
status = "disabled";
};
- amba {
+ amba: amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 07d64a8f82e3..bf092e97e14f 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -177,6 +177,20 @@
};
};
+&amba {
+ mdma0: mdma@12840000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12840000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ power-domains = <&pd_lcd0>;
+ };
+};
+
&camera {
status = "okay";
@@ -491,7 +505,8 @@
};
&mdma1 {
- reg = <0x12840000 0x1000>;
+ /* Use the secure mdma0 */
+ status = "disabled";
};
&mixer {
--
2.17.1
xusbxti fixed-clock should not have address/size cells because it does
not have any children. This also fixes DTC W=1 warning:
arch/arm/boot/dts/exynos3250.dtsi:112.21-139.5:
Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos3250.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index af54b306204b..6e74e6815b01 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -115,8 +115,6 @@
xusbxti: clock@0 {
compatible = "fixed-clock";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
clock-frequency = <0>;
#clock-cells = <0>;
--
2.17.1
On 2019-04-15 20:05, Krzysztof Kozlowski wrote:
> The ARM PMU and ARM architected timer nodes are part of ARM CPU design
> therefore they should not be inside the soc node. This also fixes DTC
> W=1 warnings like:
>
> arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5:
> Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
> arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5:
> Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Marek Szyprowski <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 12 +++++-----
> arch/arm/boot/dts/exynos4.dtsi | 12 +++++-----
> arch/arm/boot/dts/exynos5250.dtsi | 40 +++++++++++++++----------------
> arch/arm/boot/dts/exynos54xx.dtsi | 38 ++++++++++++++---------------
> 4 files changed, 51 insertions(+), 51 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 5892a9f7622f..af54b306204b 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -97,6 +97,12 @@
> };
> };
>
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> soc: soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -673,12 +679,6 @@
> status = "disabled";
> };
>
> - pmu {
> - compatible = "arm,cortex-a7-pmu";
> - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> ppmu_dmc0: ppmu_dmc0@106a0000 {
> compatible = "samsung,exynos-ppmu";
> reg = <0x106a0000 0x2000>;
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index 6085e92ac2d7..1c21627e3c3c 100644
> --- a/arch/arm/boot/dts/exynos4.dtsi
> +++ b/arch/arm/boot/dts/exynos4.dtsi
> @@ -51,6 +51,12 @@
> serial3 = &serial_3;
> };
>
> + pmu: pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupt-parent = <&combiner>;
> + interrupts = <2 2>, <3 2>;
> + };
> +
> soc: soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -169,12 +175,6 @@
> reg = <0x10440000 0x1000>;
> };
>
> - pmu: pmu {
> - compatible = "arm,cortex-a9-pmu";
> - interrupt-parent = <&combiner>;
> - interrupts = <2 2>, <3 2>;
> - };
> -
> sys_reg: syscon@10010000 {
> compatible = "samsung,exynos4-sysreg", "syscon";
> reg = <0x10010000 0x400>;
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 80986b97dfe5..96ace6a5e2f9 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -157,6 +157,26 @@
> };
> };
>
> + pmu {
> + compatible = "arm,cortex-a15-pmu";
> + interrupt-parent = <&combiner>;
> + interrupts = <1 2>, <22 4>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + /*
> + * Unfortunately we need this since some versions
> + * of U-Boot on Exynos don't set the CNTFRQ register,
> + * so we need the value from DT.
> + */
> + clock-frequency = <24000000>;
> + };
> +
> soc: soc {
> sysram@2020000 {
> compatible = "mmio-sram";
> @@ -227,20 +247,6 @@
> power-domains = <&pd_mau>;
> };
>
> - timer {
> - compatible = "arm,armv7-timer";
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> - /*
> - * Unfortunately we need this since some versions
> - * of U-Boot on Exynos don't set the CNTFRQ register,
> - * so we need the value from DT.
> - */
> - clock-frequency = <24000000>;
> - };
> -
> mct@101c0000 {
> compatible = "samsung,exynos4210-mct";
> reg = <0x101C0000 0x800>;
> @@ -265,12 +271,6 @@
> };
> };
>
> - pmu {
> - compatible = "arm,cortex-a15-pmu";
> - interrupt-parent = <&combiner>;
> - interrupts = <1 2>, <22 4>;
> - };
> -
> pinctrl_0: pinctrl@11400000 {
> compatible = "samsung,exynos5250-pinctrl";
> reg = <0x11400000 0x1000>;
> diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
> index de26e5ee0d2d..ae866bcc30c4 100644
> --- a/arch/arm/boot/dts/exynos54xx.dtsi
> +++ b/arch/arm/boot/dts/exynos54xx.dtsi
> @@ -25,27 +25,27 @@
> usbdrdphy1 = &usbdrd_phy1;
> };
>
> - soc: soc {
> - arm_a7_pmu: arm-a7-pmu {
> - compatible = "arm,cortex-a7-pmu";
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - };
> + arm_a7_pmu: arm-a7-pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
>
> - arm_a15_pmu: arm-a15-pmu {
> - compatible = "arm,cortex-a15-pmu";
> - interrupt-parent = <&combiner>;
> - interrupts = <1 2>,
> - <7 0>,
> - <16 6>,
> - <19 2>;
> - status = "disabled";
> - };
> + arm_a15_pmu: arm-a15-pmu {
> + compatible = "arm,cortex-a15-pmu";
> + interrupt-parent = <&combiner>;
> + interrupts = <1 2>,
> + <7 0>,
> + <16 6>,
> + <19 2>;
> + status = "disabled";
> + };
>
> + soc: soc {
> sysram@2020000 {
> compatible = "mmio-sram";
> reg = <0x02020000 0x54000>;
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland