From: Bartosz Golaszewski <[email protected]>
This series adds cpufreq-dt operating points for da850 boards supported
with device tree (da850-lcdk, da850-lego-ev3, da850-evm).
Last patch enables CPUFREQ_DT in davinci_all_defconfig.
v1 -> v2:
- use the VDCDC3_1.2V regulator as cpu-supply on da850-evm
v2 -> v3:
- drop patch 1, as the revision tag is in fact correctly passed to the kernel
by u-boot
- only enable the 375 operating point for da850-evm as this is the standard
frequency for this board
v3 -> v4:
- split the first patch into three separate changesets: one adding the
operating points to the main dtsi and two enabling cpufreq on da850-lego-ev3
and da850-lcdk
- remove the operating point not mentioned in the datasheet (415 MHz)
- fix commit message in patch 4/5
v4 -> v5:
- only enable a single OPP for da850-lcdk due to the problem with the OHCI
controller becoming unresponsive after cpufreq transitions
- fix the name of the pmic on da850-evm
Bartosz Golaszewski (1):
ARM: dts: da850-evm: enable cpufreq
David Lechner (4):
ARM: dts: da850: add cpu node and operating points to DT
ARM: dts: da850-lego-ev3: enable cpufreq
ARM: dts: da850-lcdk: enable cpufreq
ARM: davinci_all_defconfig: Enable CPUFREQ_DT
arch/arm/boot/dts/da850-evm.dts | 13 +++++++
arch/arm/boot/dts/da850-lcdk.dts | 36 +++++++++++++++++++
arch/arm/boot/dts/da850-lego-ev3.dts | 30 ++++++++++++++++
arch/arm/boot/dts/da850.dtsi | 50 ++++++++++++++++++++++++++
arch/arm/configs/davinci_all_defconfig | 1 +
5 files changed, 130 insertions(+)
--
2.21.0
From: Bartosz Golaszewski <[email protected]>
Enable cpufreq-dt support for da850-evm. The cvdd is supplied by the
tps65070 pmic with configurable output voltage. By default da850-evm
boards support frequencies up to 375MHz so enable this operating
point.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Adam Ford <[email protected]>
---
arch/arm/boot/dts/da850-evm.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f04bc3e15332..f94bb38fdad9 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -191,6 +191,19 @@
};
};
+&cpu {
+ cpu-supply = <&vdcdc3_reg>;
+};
+
+/*
+ * The standard da850-evm kits and SOM's are 375MHz so enable this operating
+ * point by default. Higher frequencies must be enabled for custom boards with
+ * other variants of the SoC.
+ */
+&opp_375 {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
--
2.21.0
From: David Lechner <[email protected]>
This adds a cpu node and operating points to the common da850.dtsi file.
All operating points above 300MHz are disabled by default.
Regulators need to be hooked up on a per-board basis.
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm/boot/dts/da850.dtsi | 50 ++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 559659b399d0..0c9a8e78f748 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -20,6 +20,56 @@
reg = <0xc0000000 0x0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&psc0 14>;
+ operating-points-v2 = <&opp_table>;
+ };
+ };
+
+ opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp_100: opp100-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1000000 950000 1050000>;
+ };
+
+ opp_200: opp110-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1100000 1050000 1160000>;
+ };
+
+ opp_300: opp120-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1200000 1140000 1320000>;
+ };
+
+ /*
+ * Original silicon was 300MHz max, so higher frequencies
+ * need to be enabled on a per-board basis if the chip is
+ * capable.
+ */
+
+ opp_375: opp120-375000000 {
+ status = "disabled";
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <1200000 1140000 1320000>;
+ };
+
+ opp_456: opp130-456000000 {
+ status = "disabled";
+ opp-hz = /bits/ 64 <456000000>;
+ opp-microvolt = <1300000 1250000 1350000>;
+ };
+ };
+
arm {
#address-cells = <1>;
#size-cells = <1>;
--
2.21.0
From: David Lechner <[email protected]>
This sets CONFIG_CPUFREQ_DT=m in davinci_all_defconfig. This is used for
frequency scaling on device tree boards.
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm/configs/davinci_all_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 207962a656a2..c3502236132e 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -45,6 +45,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPUFREQ_DT=m
CONFIG_CPU_IDLE=y
CONFIG_NET=y
CONFIG_PACKET=y
--
2.21.0
From: David Lechner <[email protected]>
Add a fixed regulator for the da850-lcdk board along with board-specific
CPU configuration.
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm/boot/dts/da850-lcdk.dts | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 26f453dc8370..b36d5e36bcf1 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -155,12 +155,48 @@
};
};
};
+
+ cvdd: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cvdd";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&ref_clk {
clock-frequency = <24000000>;
};
+&cpu {
+ cpu-supply = <&cvdd>;
+};
+
+/*
+ * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
+ * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
+ * can't enable more than one OPP by default, since the controller sometimes
+ * becomes unresponsive after a transition. Fix the frequency at 456 MHz.
+ */
+
+&opp_100 {
+ status = "disabled";
+};
+
+&opp_200 {
+ status = "disabled";
+};
+
+&opp_300 {
+ status = "disabled";
+};
+
+&opp_456 {
+ status = "okay";
+};
+
&pmx_core {
status = "okay";
--
2.21.0
From: David Lechner <[email protected]>
Add a fixed regulator for the LEGO EV3 board along with board-specific
CPU configuration.
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm/boot/dts/da850-lego-ev3.dts | 30 ++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
index 66fcadf0ba91..553717f84483 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -125,6 +125,15 @@
amp-supply = <&>;
};
+ cvdd: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
/*
* This is a 5V current limiting regulator that is shared by USB,
* the sensor (input) ports, the motor (output) ports and the A/DC.
@@ -204,6 +213,27 @@
clock-frequency = <24000000>;
};
+&cpu {
+ cpu-supply = <&cvdd>;
+};
+
+/* since we have a fixed regulator, we can't run at these points */
+&opp_100 {
+ status = "disabled";
+};
+
+&opp_200 {
+ status = "disabled";
+};
+
+/*
+ * The SoC is actually the 456MHz version, but because of the fixed regulator
+ * This is the fastest we can go.
+ */
+&opp_375 {
+ status = "okay";
+};
+
&pmx_core {
status = "okay";
--
2.21.0
On Wed, Apr 17, 2019 at 10:27 AM Bartosz Golaszewski <[email protected]> wrote:
>
> From: Bartosz Golaszewski <[email protected]>
>
> Enable cpufreq-dt support for da850-evm. The cvdd is supplied by the
> tps65070 pmic with configurable output voltage. By default da850-evm
> boards support frequencies up to 375MHz so enable this operating
> point.
Have you done any testing with the LCD on any of the devices you have?
I enabled the ondemand governor, and I got a bunch of splat from the
LCD controller:
tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
differs from the calculated rate (54000000Hz)
tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
... [ snip]
tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
differs from the calculated rate (54000000Hz)
tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
differs from the calculated rate (54000000Hz)
tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
It appears to go on forever. I don't necessarily want to hold it up,
but I don't know the clocking system well enough to know where to go
investigate it. I can certainly live without ondemand. Using
userspace as the default governor is fine for me for now.
adam
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> Reviewed-by: Adam Ford <[email protected]>
> ---
> arch/arm/boot/dts/da850-evm.dts | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> index f04bc3e15332..f94bb38fdad9 100644
> --- a/arch/arm/boot/dts/da850-evm.dts
> +++ b/arch/arm/boot/dts/da850-evm.dts
> @@ -191,6 +191,19 @@
> };
> };
>
> +&cpu {
> + cpu-supply = <&vdcdc3_reg>;
> +};
> +
> +/*
> + * The standard da850-evm kits and SOM's are 375MHz so enable this operating
> + * point by default. Higher frequencies must be enabled for custom boards with
> + * other variants of the SoC.
> + */
> +&opp_375 {
> + status = "okay";
> +};
> +
> &sata {
> status = "okay";
> };
> --
> 2.21.0
>
śr., 17 kwi 2019 o 19:09 Adam Ford <[email protected]> napisał(a):
>
> On Wed, Apr 17, 2019 at 10:27 AM Bartosz Golaszewski <[email protected]> wrote:
> >
> > From: Bartosz Golaszewski <[email protected]>
> >
> > Enable cpufreq-dt support for da850-evm. The cvdd is supplied by the
> > tps65070 pmic with configurable output voltage. By default da850-evm
> > boards support frequencies up to 375MHz so enable this operating
> > point.
>
> Have you done any testing with the LCD on any of the devices you have?
>
> I enabled the ondemand governor, and I got a bunch of splat from the
> LCD controller:
>
> tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> differs from the calculated rate (54000000Hz)
> tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
> tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
> ... [ snip]
> tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> differs from the calculated rate (54000000Hz)
> tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> differs from the calculated rate (54000000Hz)
> tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
>
> It appears to go on forever. I don't necessarily want to hold it up,
> but I don't know the clocking system well enough to know where to go
> investigate it. I can certainly live without ondemand. Using
> userspace as the default governor is fine for me for now.
>
> adam
Hi Adam,
I did test the tilcdc on da850-lcdk. The only message I'm getting
during transitions is a single:
tilcdc <name>: tilcdc_crtc_irq(<address>): FIFO underflow
but this is fairly normal - we also get this during modeset and it
doesn't affect the display.
The problem with the pixel clock may come from the bootloader - are
you using a recent version of u-boot?
Bart
> >
> > Signed-off-by: Bartosz Golaszewski <[email protected]>
> > Reviewed-by: Adam Ford <[email protected]>
> > ---
> > arch/arm/boot/dts/da850-evm.dts | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> > index f04bc3e15332..f94bb38fdad9 100644
> > --- a/arch/arm/boot/dts/da850-evm.dts
> > +++ b/arch/arm/boot/dts/da850-evm.dts
> > @@ -191,6 +191,19 @@
> > };
> > };
> >
> > +&cpu {
> > + cpu-supply = <&vdcdc3_reg>;
> > +};
> > +
> > +/*
> > + * The standard da850-evm kits and SOM's are 375MHz so enable this operating
> > + * point by default. Higher frequencies must be enabled for custom boards with
> > + * other variants of the SoC.
> > + */
> > +&opp_375 {
> > + status = "okay";
> > +};
> > +
> > &sata {
> > status = "okay";
> > };
> > --
> > 2.21.0
> >
wt., 23 kwi 2019 o 11:15 Bartosz Golaszewski
<[email protected]> napisał(a):
>
> śr., 17 kwi 2019 o 19:09 Adam Ford <[email protected]> napisał(a):
> >
> > On Wed, Apr 17, 2019 at 10:27 AM Bartosz Golaszewski <[email protected]> wrote:
> > >
> > > From: Bartosz Golaszewski <[email protected]>
> > >
> > > Enable cpufreq-dt support for da850-evm. The cvdd is supplied by the
> > > tps65070 pmic with configurable output voltage. By default da850-evm
> > > boards support frequencies up to 375MHz so enable this operating
> > > point.
> >
> > Have you done any testing with the LCD on any of the devices you have?
> >
> > I enabled the ondemand governor, and I got a bunch of splat from the
> > LCD controller:
> >
> > tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> > differs from the calculated rate (54000000Hz)
> > tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
> > tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
> > ... [ snip]
> > tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> > differs from the calculated rate (54000000Hz)
> > tilcdc 1e13000.display: effective pixel clock rate (50000000Hz)
> > differs from the calculated rate (54000000Hz)
> > tilcdc 1e13000.display: tilcdc_crtc_irq(0x00000161): FIFO underflow
> >
> > It appears to go on forever. I don't necessarily want to hold it up,
> > but I don't know the clocking system well enough to know where to go
> > investigate it. I can certainly live without ondemand. Using
> > userspace as the default governor is fine for me for now.
> >
> > adam
>
> Hi Adam,
>
> I did test the tilcdc on da850-lcdk. The only message I'm getting
> during transitions is a single:
>
> tilcdc <name>: tilcdc_crtc_irq(<address>): FIFO underflow
>
> but this is fairly normal - we also get this during modeset and it
> doesn't affect the display.
>
> The problem with the pixel clock may come from the bootloader - are
> you using a recent version of u-boot?
>
> Bart
>
> > >
> > > Signed-off-by: Bartosz Golaszewski <[email protected]>
> > > Reviewed-by: Adam Ford <[email protected]>
> > > ---
> > > arch/arm/boot/dts/da850-evm.dts | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> > > index f04bc3e15332..f94bb38fdad9 100644
> > > --- a/arch/arm/boot/dts/da850-evm.dts
> > > +++ b/arch/arm/boot/dts/da850-evm.dts
> > > @@ -191,6 +191,19 @@
> > > };
> > > };
> > >
> > > +&cpu {
> > > + cpu-supply = <&vdcdc3_reg>;
> > > +};
> > > +
> > > +/*
> > > + * The standard da850-evm kits and SOM's are 375MHz so enable this operating
> > > + * point by default. Higher frequencies must be enabled for custom boards with
> > > + * other variants of the SoC.
> > > + */
> > > +&opp_375 {
> > > + status = "okay";
> > > +};
> > > +
> > > &sata {
> > > status = "okay";
> > > };
> > > --
> > > 2.21.0
> > >
Hi Adam,
did you figure out the problem by chance? Are you OK with merging this series?
Bart