Hello, here are two trivial patches that are correcting PLLM on Tegra124.
First fixes system lockup due to a bad hardware configuration, second
removes usage of a non-existent register bit.
Dmitry Osipenko (2):
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides
divider
clk: tegra124: Remove lock-enable bit from PLLM
drivers/clk/tegra/clk-pll.c | 4 ++--
drivers/clk/tegra/clk-tegra124.c | 3 +--
2 files changed, 3 insertions(+), 4 deletions(-)
--
2.21.0
According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't
have the lock-enable bit as well as any other PLLM-related register. Hence
PLLM re-locking can't be initiated by software. The incorrect bit setting
should have been harmless since that bit is undefined according to TRM.
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/clk/tegra/clk-tegra124.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index df0018f7bf7e..940592375583 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -413,7 +413,6 @@ static struct tegra_clk_pll_params pll_m_params = {
.base_reg = PLLM_BASE,
.misc_reg = PLLM_MISC,
.lock_mask = PLL_BASE_LOCK,
- .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300,
.max_p = 5,
.pdiv_tohw = pllm_p,
@@ -421,7 +420,7 @@ static struct tegra_clk_pll_params pll_m_params = {
.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
.freq_table = pll_m_freq_table,
- .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+ .flags = TEGRA_PLL_USE_LOCK,
};
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
--
2.21.0
There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.
Cc: <[email protected]>
Tested-by: Steev Klimaszewski <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/clk/tegra/clk-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b50b7460014b..3e67cbcd80da 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -663,8 +663,8 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
pll_override_writel(val, params->pmc_divp_reg, pll);
val = pll_override_readl(params->pmc_divnm_reg, pll);
- val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
- ~(divn_mask(pll) << div_nmp->override_divn_shift);
+ val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
+ (divn_mask(pll) << div_nmp->override_divn_shift));
val |= (cfg->m << div_nmp->override_divm_shift) |
(cfg->n << div_nmp->override_divn_shift);
pll_override_writel(val, params->pmc_divnm_reg, pll);
--
2.21.0
12.04.2019 0:48, Dmitry Osipenko пишет:
> Hello, here are two trivial patches that are correcting PLLM on Tegra124.
> First fixes system lockup due to a bad hardware configuration, second
> removes usage of a non-existent register bit.
>
> Dmitry Osipenko (2):
> clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides
> divider
> clk: tegra124: Remove lock-enable bit from PLLM
>
> drivers/clk/tegra/clk-pll.c | 4 ++--
> drivers/clk/tegra/clk-tegra124.c | 3 +--
> 2 files changed, 3 insertions(+), 4 deletions(-)
>
Hello Peter,
The patches in this series are trivial and fixing the longstanding bug on Tegra124. Could you please take a look and and ACK the series if it looks good to you?
On Fri, Apr 19, 2019 at 02:50:10PM +0300, Dmitry Osipenko wrote:
> 12.04.2019 0:48, Dmitry Osipenko пишет:
> > Hello, here are two trivial patches that are correcting PLLM on Tegra124.
> > First fixes system lockup due to a bad hardware configuration, second
> > removes usage of a non-existent register bit.
> >
> > Dmitry Osipenko (2):
> > clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides
> > divider
> > clk: tegra124: Remove lock-enable bit from PLLM
> >
> > drivers/clk/tegra/clk-pll.c | 4 ++--
> > drivers/clk/tegra/clk-tegra124.c | 3 +--
> > 2 files changed, 3 insertions(+), 4 deletions(-)
> >
>
> Hello Peter,
>
> The patches in this series are trivial and fixing the longstanding bug on Tegra124. Could you please take a look and and ACK the series if it looks good to you?
Acked-By: Peter De Schrijver <[email protected]>
Peter.
24.04.2019 11:36, Peter De Schrijver пишет:
> On Fri, Apr 19, 2019 at 02:50:10PM +0300, Dmitry Osipenko wrote:
>> 12.04.2019 0:48, Dmitry Osipenko пишет:
>>> Hello, here are two trivial patches that are correcting PLLM on Tegra124.
>>> First fixes system lockup due to a bad hardware configuration, second
>>> removes usage of a non-existent register bit.
>>>
>>> Dmitry Osipenko (2):
>>> clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides
>>> divider
>>> clk: tegra124: Remove lock-enable bit from PLLM
>>>
>>> drivers/clk/tegra/clk-pll.c | 4 ++--
>>> drivers/clk/tegra/clk-tegra124.c | 3 +--
>>> 2 files changed, 3 insertions(+), 4 deletions(-)
>>>
>>
>> Hello Peter,
>>
>> The patches in this series are trivial and fixing the longstanding bug on Tegra124. Could you please take a look and and ACK the series if it looks good to you?
>
> Acked-By: Peter De Schrijver <[email protected]>
Thank you, Peter.
Stephen, is yours maintainer-tool able to pick up the "Acked-By" for the whole series or do I need to resend the series with a proper "Acked-by" tag added to every patch? Please let me know.
Quoting Dmitry Osipenko (2019-04-25 06:50:39)
> 24.04.2019 11:36, Peter De Schrijver пишет:
> > On Fri, Apr 19, 2019 at 02:50:10PM +0300, Dmitry Osipenko wrote:
> >> 12.04.2019 0:48, Dmitry Osipenko пишет:
> >>
> >> The patches in this series are trivial and fixing the longstanding bug on Tegra124. Could you please take a look and and ACK the series if it looks good to you?
> >
> > Acked-By: Peter De Schrijver <[email protected]>
>
> Thank you, Peter.
>
>
> Stephen, is yours maintainer-tool able to pick up the "Acked-By" for the whole series or do I need to resend the series with a proper "Acked-by" tag added to every patch? Please let me know.
The maintainer-tool is me, but I don't require you to resend to collect
acks or other tags. I can do it and I'll do it today.
Quoting Dmitry Osipenko (2019-04-11 14:48:35)
> According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't
> have the lock-enable bit as well as any other PLLM-related register. Hence
> PLLM re-locking can't be initiated by software. The incorrect bit setting
> should have been harmless since that bit is undefined according to TRM.
>
> Tested-by: Steev Klimaszewski <[email protected]>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---
Applied to clk-next
25.04.2019 18:14, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2019-04-25 06:50:39)
>> 24.04.2019 11:36, Peter De Schrijver пишет:
>>> On Fri, Apr 19, 2019 at 02:50:10PM +0300, Dmitry Osipenko wrote:
>>>> 12.04.2019 0:48, Dmitry Osipenko пишет:
>>>>
>>>> The patches in this series are trivial and fixing the longstanding bug on Tegra124. Could you please take a look and and ACK the series if it looks good to you?
>>>
>>> Acked-By: Peter De Schrijver <[email protected]>
>>
>> Thank you, Peter.
>>
>>
>> Stephen, is yours maintainer-tool able to pick up the "Acked-By" for the whole series or do I need to resend the series with a proper "Acked-by" tag added to every patch? Please let me know.
>
> The maintainer-tool is me, but I don't require you to resend to collect
> acks or other tags. I can do it and I'll do it today.
>
Thank you very much!
Quoting Dmitry Osipenko (2019-04-11 14:48:34)
> There are wrongly set parenthesis in the code that are resulting in a
> wrong configuration being programmed for PLLM. The original fix was made
> by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
> Tegra124 chromebook, PLLM rate changing works correctly now and system
> doesn't lock up after changing the PLLM rate due to EMC scaling.
>
> Cc: <[email protected]>
> Tested-by: Steev Klimaszewski <[email protected]>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---
Applied to clk-next