The patchsets add support for MediaTek hardware module named DVFSRC
(dynamic voltage and frequency scaling resource collector). The DVFSRC is
a HW module which is used to collect all the requests from both software
and hardware and turn into the decision of minimum operating voltage and
minimum DRAM frequency to fulfill those requests.
So, This series is to implement the dvfsrc driver to collect all the
requests of operating voltage or DRAM bandwidth from other device drivers
likes GPU/Camera through 2 frameworks basically:
1. interconnect framework: to aggregate the bandwidth
requirements from different clients
[1] https://patchwork.kernel.org/cover/10766329/
Below is the emi bandwidth map of mt8183. There has a hw module "DRAM scheduler"
which used to control the throughput. The DVFSRC will collect forecast data
of dram bandwidth from SW consumers(camera/gpu...), and according the forecast
to change the DRAM frequency
ICC provider ICC Nodes
---- ----
--------- |CPU | |--->|VPU |
----- | |-----> ---- | ----
|DRAM |--|DRAM | ---- | ----
| |--|scheduler|----->|GPU | |--->|DISP|
| |--|(EMI) | ---- | ----
| |--| | ----- | ----
----- | |----->|MMSYS|--|--->|VDEC|
--------- ----- | ----
/|\ | ----
|change DRAM freq |--->|VENC|
---------- | ----
| DVFSR | |
| | | ----
---------- |--->|IMG |
| ----
| ----
|--->|CAM |
----
2. Active state management of power domains[1]: to handle the operating
voltage opp requirement from different power domains
[2] https://lwn.net/Articles/744047/
Changes in RFC V2:
* Remove the DT property dram_type. (Rob)
* Used generic dts property 'opp-level' to get the performace state. (Stephen)
* Remove unecessary dependency config on Kconfig. (Stephen)
* Remove unused header file, fixed some coding style issue, typo,
error handling on dvfsrc driver. (Nicolas/Stephen)
* Remove irq handler on dvfsrc driver. (Stephen)
* Remove init table on dvfsrc driver, combine hw init on trustzone.
* Add interconnect support of mt8183 to aggregate the emi bandwidth.
(Georgi)
RFC V1: https://lore.kernel.org/patchwork/cover/1028535/
Henry Chen (11):
dt-bindings: soc: Add dvfsrc driver bindings
dt-bindings: soc: Add opp table on scpsys bindings
soc: mediatek: add support for the performance state
arm64: dts: mt8183: add performance state support of scpsys
soc: mediatek: add header for mediatek SIP interface
soc: mediatek: add MT8183 dvfsrc support
arm64: dts: mt8183: add dvfsrc related nodes
dt-bindings: interconnect: add MT8183 interconnect dt-bindings
dt-bindings: interconnect: Add header for interconnect node
interconnect: mediatek: Add mt8183 interconnect provider driver
arm64: dts: mt8183: Add interconnect provider DT nodes
.../bindings/interconnect/mtk,mt8183.txt | 24 ++
.../devicetree/bindings/soc/mediatek/dvfsrc.txt | 23 ++
.../devicetree/bindings/soc/mediatek/scpsys.txt | 42 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 33 ++
drivers/interconnect/Kconfig | 1 +
drivers/interconnect/Makefile | 1 +
drivers/interconnect/mediatek/Kconfig | 13 +
drivers/interconnect/mediatek/Makefile | 5 +
drivers/interconnect/mediatek/mt8183.c | 223 +++++++++++++
drivers/soc/mediatek/Kconfig | 15 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mtk-dvfsrc.c | 347 +++++++++++++++++++++
drivers/soc/mediatek/mtk-scpsys.c | 53 ++++
drivers/soc/mediatek/mtk-scpsys.h | 22 ++
include/dt-bindings/interconnect/mtk,mt8183.h | 18 ++
include/dt-bindings/soc/mtk,dvfsrc.h | 14 +
include/soc/mediatek/mtk_dvfsrc.h | 22 ++
include/soc/mediatek/mtk_sip.h | 17 +
18 files changed, 874 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mtk,mt8183.txt
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt
create mode 100644 drivers/interconnect/mediatek/Kconfig
create mode 100644 drivers/interconnect/mediatek/Makefile
create mode 100644 drivers/interconnect/mediatek/mt8183.c
create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
create mode 100644 include/dt-bindings/interconnect/mtk,mt8183.h
create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h
create mode 100644 include/soc/mediatek/mtk_dvfsrc.h
create mode 100644 include/soc/mediatek/mtk_sip.h
--
1.9.1
Add opp table on scpsys dt-bindings for Mediatek SoC.
Signed-off-by: Henry Chen <[email protected]>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index b4728ce..33df802 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -63,6 +63,10 @@ Optional properties:
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
+- operating-points-v2: Phandle to the OPP table for the Power domain.
+ Refer to Documentation/devicetree/bindings/power/power_domain.txt
+ and Documentation/devicetree/bindings/opp/opp.txt for more details
+
Example:
scpsys: scpsys@10006000 {
@@ -75,6 +79,27 @@ Example:
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
+ operating-points-v2 = <&dvfsrc_opp_table>;
+
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = <MT8183_DVFSRC_LEVEL_1>;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = <MT8183_DVFSRC_LEVEL_2>;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = <MT8183_DVFSRC_LEVEL_3>;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = <MT8183_DVFSRC_LEVEL_4>;
+ };
+ };
};
Example consumer:
@@ -82,4 +107,21 @@ Example consumer:
afe: mt8173-afe-pcm@11220000 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ operating-points-v2 = <&aud_opp_table>;
+ };
+
+ aud_opp_table: aud-opp-table {
+ compatible = "operating-points-v2";
+ opp1 {
+ opp-hz = /bits/ 64 <793000000>;
+ required-opps = <&dvfsrc_vol_min>;
+ };
+ opp2 {
+ opp-hz = /bits/ 64 <910000000>;
+ required-opps = <&dvfsrc_vol_max>;
+ };
+ opp3 {
+ opp-hz = /bits/ 64 <1014000000>;
+ required-opps = <&dvfsrc_vol_max>;
+ };
};
--
1.9.1
Enable dvfsrc on mt8183 platform.
Signed-off-by: Henry Chen <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 665d561..d298013 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -134,6 +134,13 @@
clock-output-names = "clk26m";
};
+ dvfsrc@10012000 {
+ compatible = "mediatek,mt8183-dvfsrc";
+ reg = <0 0x10012000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DVFSRC>;
+ clock-names = "dvfsrc";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
--
1.9.1
On Tue, 30 Apr 2019 16:50:56 +0800, Henry Chen wrote:
> Add opp table on scpsys dt-bindings for Mediatek SoC.
>
> Signed-off-by: Henry Chen <[email protected]>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>