Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
v3:
- Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
of renesas,gic-spi-base,
v2:
- Add "renesas,gic-spi-base",
- Document RZ/A2M.
---
.../renesas,rza1-irqc.txt | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
new file mode 100644
index 0000000000000000..727b7e4cd6e01110
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
@@ -0,0 +1,43 @@
+DT bindings for the Renesas RZ/A1 Interrupt Controller
+
+The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
+RZ/A1 and RZ/A2 SoCs:
+ - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
+ interrupts,
+ - NMI edge select.
+
+Required properties:
+ - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
+ fallback.
+ Examples with soctypes are:
+ - "renesas,r7s72100-irqc" (RZ/A1H)
+ - "renesas,r7s9210-irqc" (RZ/A2M)
+ - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
+ in interrupts.txt in this directory)
+ - #address-cells: Must be zero
+ - interrupt-controller: Marks the device as an interrupt controller
+ - reg: Base address and length of the memory resource used by the interrupt
+ controller
+ - interrupt-map: Specifies the mapping from external interrupts to GIC
+ interrupts
+ - interrupt-map-mask: Must be <7 0>
+
+Example:
+
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
--
2.17.1
On Thu, May 02, 2019 at 02:32:16PM +0200, Geert Uytterhoeven wrote:
> Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
On Tue, May 07, 2019 at 03:51:44PM +0200, Simon Horman wrote:
> On Thu, May 02, 2019 at 02:32:16PM +0200, Geert Uytterhoeven wrote:
> > Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
> >
> > Signed-off-by: Geert Uytterhoeven <[email protected]>
>
> Reviewed-by: Simon Horman <[email protected]>
FWIIW, Acceptance/Approval of this patch is blocking me
applying the soc and dt patches of this series.
On Thu, 2 May 2019 14:32:16 +0200, Geert Uytterhoeven wrote:
> Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
> ---
> v3:
> - Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
> of renesas,gic-spi-base,
>
> v2:
> - Add "renesas,gic-spi-base",
> - Document RZ/A2M.
> ---
> .../renesas,rza1-irqc.txt | 43 +++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
>
Reviewed-by: Rob Herring <[email protected]>
Hi Rob,
On Thu, May 2, 2019 at 2:32 PM Geert Uytterhoeven
<[email protected]> wrote:
> Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
> @@ -0,0 +1,43 @@
> +DT bindings for the Renesas RZ/A1 Interrupt Controller
> +
> +The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
> +RZ/A1 and RZ/A2 SoCs:
> + - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
> + interrupts,
> + - NMI edge select.
> +
> +Required properties:
> + - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
> + fallback.
> + Examples with soctypes are:
> + - "renesas,r7s72100-irqc" (RZ/A1H)
> + - "renesas,r7s9210-irqc" (RZ/A2M)
> + - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
> + in interrupts.txt in this directory)
> + - #address-cells: Must be zero
> + - interrupt-controller: Marks the device as an interrupt controller
> + - reg: Base address and length of the memory resource used by the interrupt
> + controller
> + - interrupt-map: Specifies the mapping from external interrupts to GIC
> + interrupts
> + - interrupt-map-mask: Must be <7 0>
> +
> +Example:
> +
> + irqc: interrupt-controller@fcfef800 {
> + compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0xfcfef800 0x6>;
> + interrupt-map =
> + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map-mask = <7 0>;
> + };
"make dtbs_check" does not like this example:
arch/arm/boot/dts/r7s72100-rskrza1.dt.yaml:
interrupt-controller@fcfef800: {'compatible':
['renesas,r7s72100-irqc', 'renesas,rza1-irqc'], '#interrupt-cells':
[[2]], '#address-cells': [[0]], 'interrupt-controller': True, 'reg':
[[4244568064, 6]], 'interrupt-map': [[0, 0, 3, 0, 0, 4], [1, 0, 3, 0,
1, 4], [2, 0, 3, 0, 2, 4], [3, 0, 3, 0, 3, 4], [4, 0, 3, 0, 4, 4], [5,
0, 3, 0, 5, 4], [6, 0, 3, 0, 6, 4], [7, 0, 3, 0, 7, 4]],
'interrupt-map-mask': [[7, 0]], 'phandle': [[27]], '$nodename':
['interrupt-controller@fcfef800']} is valid under each of {'required':
['interrupt-map']}, {'required': ['interrupt-controller']}
{'oneOf': [{'required': ['interrupt-controller']},
{'required': ['interrupt-map']}]}
as it considers interrupt-controller and interrupt-map mutually-exclusive.
This comes from
dt-schema/meta-schemas/interrupts.yaml:
dependencies:
interrupt-map: ['#interrupt-cells', 'interrupt-map-mask']
'#interrupt-cells':
oneOf:
- required:
- interrupt-controller
- required:
- interrupt-map
and/or dt-schema/schemas/interrupt-controller.yaml:
dependencies:
interrupt-controller: ['#interrupt-cells']
interrupt-map: ['#interrupt-cells', 'interrupt-map-mask']
"#interrupt-cells":
oneOf:
- required:
- interrupt-controller
- required:
- interrupt-map
Removing the "interrupt-controller" property fixes the warning, but
impacts the logic in of_irq_parse_raw().
Is there something wrong with the base schema?
Or perhaps this will just be be fixed by converting renesas,rza1-irqc.txt
to yaml?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds