The GPIO Input Buffer Enable register is used to control the input
enable of each individual GPIO port. When an individual GPIO port's
direction is set to input (GPIO_GPDIR[DRn=0]), the associated
input enable must be set (GPIOxGPIE[IEn]=1) to propagate the port
value to the GPIO Data Register.
This patch enable port input and interrupt.
Signed-off-by: Zhang Ying-22455 <[email protected]>
Signed-off-by: Chuanhua Han <[email protected]>
---
drivers/gpio/gpio-mpc8xxx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index c8673a5d9412..555e0e7957d9 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -373,9 +373,10 @@ static int mpc8xxx_probe(struct platform_device *pdev)
if (!mpc8xxx_gc->irq)
return 0;
- /* ack and mask all irqs */
+ /* ack and enable irqs */
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
- gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
+ gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0xffffffff);
+ gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR2, 0xffffffff);
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
--
2.17.1
Since fsl-ls1088a Soc GPIO registers are used as little endian,
the patch adds the little-endian attribute to each gpio node.
Signed-off-by: Chuanhua Han <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137ffa319..3e6d20d065bd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -272,6 +272,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -282,6 +283,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -292,6 +294,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -302,6 +305,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.17.1
On Wed, May 29, 2019 at 3:33 AM Chuanhua Han <[email protected]> wrote:
>
> The GPIO Input Buffer Enable register is used to control the input
> enable of each individual GPIO port. When an individual GPIO port's
> direction is set to input (GPIO_GPDIR[DRn=0]), the associated
> input enable must be set (GPIOxGPIE[IEn]=1) to propagate the port
> value to the GPIO Data Register.
I cannot relate what you are saying here with the code you changed.
>
> This patch enable port input and interrupt.
NACK
Why do we need to unmask all the interrupts by default? The correct
behavior is that all interrupts masked until they are actually
requested.
>
> Signed-off-by: Zhang Ying-22455 <[email protected]>
> Signed-off-by: Chuanhua Han <[email protected]>
> ---
> drivers/gpio/gpio-mpc8xxx.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
> index c8673a5d9412..555e0e7957d9 100644
> --- a/drivers/gpio/gpio-mpc8xxx.c
> +++ b/drivers/gpio/gpio-mpc8xxx.c
> @@ -373,9 +373,10 @@ static int mpc8xxx_probe(struct platform_device *pdev)
> if (!mpc8xxx_gc->irq)
> return 0;
>
> - /* ack and mask all irqs */
> + /* ack and enable irqs */
> gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
> - gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
> + gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0xffffffff);
> + gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR2, 0xffffffff);
>
> irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
> mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
> --
> 2.17.1
>
On Wed, May 29, 2019 at 3:32 AM Chuanhua Han <[email protected]> wrote:
>
> Since fsl-ls1088a Soc GPIO registers are used as little endian,
> the patch adds the little-endian attribute to each gpio node.
>
> Signed-off-by: Chuanhua Han <[email protected]>
Acked-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index 661137ffa319..3e6d20d065bd 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -272,6 +272,7 @@
> compatible = "fsl,qoriq-gpio";
> reg = <0x0 0x2300000 0x0 0x10000>;
> interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -282,6 +283,7 @@
> compatible = "fsl,qoriq-gpio";
> reg = <0x0 0x2310000 0x0 0x10000>;
> interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -292,6 +294,7 @@
> compatible = "fsl,qoriq-gpio";
> reg = <0x0 0x2320000 0x0 0x10000>;
> interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -302,6 +305,7 @@
> compatible = "fsl,qoriq-gpio";
> reg = <0x0 0x2330000 0x0 0x10000>;
> interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> --
> 2.17.1
>
On Wed, May 29, 2019 at 04:32:54PM +0800, Chuanhua Han wrote:
> Since fsl-ls1088a Soc GPIO registers are used as little endian,
> the patch adds the little-endian attribute to each gpio node.
>
> Signed-off-by: Chuanhua Han <[email protected]>
Applied, thanks.