2019-06-02 08:06:38

by Paul Walmsley

Subject: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed

Add initial board data for the SiFive HiFive Unleashed A00.

Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.

This third version incorporates changes based on more comments from
Rob Herring <[email protected]>.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/riscv/boot/dts/sifive/Makefile | 2 +
.../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++
2 files changed, 69 insertions(+)
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
new file mode 100644
index 000000000000..baaeef9efdcb
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-y += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
new file mode 100644
index 000000000000..1de4ea1577d5
--- /dev/null
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include "fu540-c000.dtsi"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unleashed A00";
+ compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+ chosen {
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+};
+
+&qspi0 {
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&qspi2 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
--
2.20.1

2019-06-04 14:42:56

by Loys Ollivier

Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed

On Sun 02 Jun 2019 at 01:05, Paul Walmsley <[email protected]> wrote:

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <[email protected]>.
>
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
Tested-by: Loys Ollivier <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]

2019-06-09 06:21:52

by Antony Pavlov

Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed

On Sun, 2 Jun 2019 01:05:00 -0700
Paul Walmsley <[email protected]> wrote:

Hi!

> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> This third version incorporates changes based on more comments from
> Rob Herring <[email protected]>.
>
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Albert Ou <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> arch/riscv/boot/dts/sifive/Makefile | 2 +
> .../boot/dts/sifive/hifive-unleashed-a00.dts | 67 +++++++++++++++++++
> 2 files changed, 69 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/Makefile
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
>
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..baaeef9efdcb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-y += hifive-unleashed-a00.dtb
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> new file mode 100644
> index 000000000000..1de4ea1577d5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"

You already have "/dts-v1/;" in the fu540-c000.dtsi file.

You can omit it in the hifive-unleashed-a00.dts file.

> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ 1000000
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SiFive HiFive Unleashed A00";
> + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
> +
> + chosen {
> + };
> +
> + cpus {
> + timebase-frequency = <RTCCLK_FREQ>;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x2 0x00000000>;
> + };
> +
> + soc {
> + };
> +
> + hfclk: hfclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <33333333>;
> + clock-output-names = "hfclk";
> + };
> +
> + rtcclk: rtcclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <RTCCLK_FREQ>;
> + clock-output-names = "rtcclk";
> + };
> +};
> +
> +&qspi0 {
> + flash@0 {
> + compatible = "issi,is25wp256", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <50000000>;
> + m25p,fast-read;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + };
> +};
> +
> +&qspi2 {
> + status = "okay";
> + mmc@0 {
> + compatible = "mmc-spi-slot";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + voltage-ranges = <3300 3300>;
> + disable-wp;
> + };
> +};
> --
> 2.20.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv


--
Best regards,
? Antony Pavlov

2019-06-16 18:37:09

by Paul Walmsley

Subject: Re: [PATCH v3 5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed

On Sun, 9 Jun 2019, Antony Pavlov wrote:

> On Sun, 2 Jun 2019 01:05:00 -0700
> Paul Walmsley <[email protected]> wrote:
>
> Hi!
>
> > Add initial board data for the SiFive HiFive Unleashed A00.

...

> > new file mode 100644
> > index 000000000000..1de4ea1577d5
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
> > @@ -0,0 +1,67 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2018-2019 SiFive, Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "fu540-c000.dtsi"
>
> You already have "/dts-v1/;" in the fu540-c000.dtsi file.
>
> You can omit it in the hifive-unleashed-a00.dts file.

Thanks for the comment. Dropped the line, per your suggestion.


- Paul