2019-06-25 07:47:42

by Anson Huang

Subject: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

From: Anson Huang <[email protected]>

i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.

Signed-off-by: Anson Huang <[email protected]>
---
drivers/clk/imx/clk-imx8mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 516e68d..d1a84f7 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };

static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
- "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };
+ "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };

static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
--
2.7.4

2019-06-25 07:48:38

by Jacky Bai

Subject: RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

OK for me.

BR
Jacky Bai
> -----Original Message-----
> From: [email protected] [mailto:[email protected]]
> Sent: Tuesday, June 25, 2019 3:06 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> Leonard Crestez <[email protected]>; Jacky Bai <[email protected]>;
> Peng Fan <[email protected]>; [email protected];
> [email protected]; [email protected]
> Cc: dl-linux-imx <[email protected]>
> Subject: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be
> sys_pll1_80m
>
> From: Anson Huang <[email protected]>
>
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> sys_pll1_800m, correct it.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> drivers/clk/imx/clk-imx8mm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 516e68d..d1a84f7 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] =
> {"osc_24m", "sys_pll2_100m", "sys_pll1_1
> "sys_pll3_out", "clk_ext2", "sys_pll1_80m",
> "video_pll1_out", };
>
> static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m",
> "sys_pll1_400m", "sys_pll1_40m",
> - "video_pll1_out", "sys_pll1_800m",
> "audio_pll1_out", "clk_ext1" };
> + "video_pll1_out", "sys_pll1_80m", "audio_pll1_out",
> "clk_ext1" };
>
> static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m",
> "sys_pll1_160m", "vpu_pll_out",
> "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m",
> "sys_pll2_166m", };
> --
> 2.7.4

2019-06-25 20:39:32

by Stephen Boyd

Subject: Re: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

Quoting [email protected] (2019-06-25 00:06:02)
> From: Anson Huang <[email protected]>
>
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
> NOT sys_pll1_800m, correct it.
>
> Signed-off-by: Anson Huang <[email protected]>

Any Fixes tags?

2019-06-26 01:28:24

by Anson Huang

Subject: RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

Hi, Stephen

> Quoting [email protected] (2019-06-25 00:06:02)
> > From: Anson Huang <[email protected]>
> >
> > i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> > sys_pll1_800m, correct it.
> >
> > Signed-off-by: Anson Huang <[email protected]>
>
> Any Fixes tags?

Oops, I forgot to add fixed tags, just resent the patch set, sorry for that.

Thanks,
Anson