This patchset ports CPU clock detection for MT7621 from OpenWrt.
Last time I sent this, I forgot to add an binding include which
caused a compile error and the patch doesn't stay in linux-next.
This patchset resent the first two commits and also added binding
documentation for mt7621-pll and used it in mt7621-dts at
drivers/staging.
BTW: What should I do with such a patchset that touches multiple
parts in kernel?
Is it correct to send the entire patchset to lists of all involved
subsystems?
Chuanhong Guo (5):
MIPS: ralink: add dt binding header for mt7621-pll
MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices
dt: bindings: add mt7621-pll dt binding documentation
staging: mt7621-dts: add dt nodes for mt7621-pll
staging: mt7621-dts: fix register range of memc node in mt7621.dtsi
.../bindings/clock/mediatek,mt7621-pll.txt | 19 ++++
arch/mips/include/asm/mach-ralink/mt7621.h | 20 ++++
arch/mips/ralink/mt7621.c | 102 ++++++++++++------
arch/mips/ralink/timer-gic.c | 4 +-
drivers/staging/mt7621-dts/mt7621.dtsi | 17 ++-
include/dt-bindings/clock/mt7621-clk.h | 14 +++
6 files changed, 134 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
--
2.21.0
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao <[email protected]>
Signed-off-by: Chuanhong Guo <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..a29e14ee2efe
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Weijie Gao <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_MT7621_CLK_H
+#define __DT_BINDINGS_MT7621_CLK_H
+
+#define MT7621_CLK_CPU 0
+#define MT7621_CLK_BUS 1
+
+#define MT7621_CLK_MAX 2
+
+#endif /* __DT_BINDINGS_MT7621_CLK_H */
--
2.21.0
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo <[email protected]>
---
.../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
new file mode 100644
index 000000000000..05c15062cd20
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
@@ -0,0 +1,19 @@
+Binding for Mediatek MT7621 PLL controller
+
+The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
+
+Required Properties:
+- compatible: has to be "mediatek,mt7621-pll"
+- #clock-cells: has to be one
+
+Optional properties:
+- clock-output-names: should be "cpu", "bus"
+
+Example:
+ pll {
+ compatible = "mediatek,mt7621-pll", "syscon";
+
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "bus";
+ };
+
--
2.21.0
This commit adds device-tree node for mt7621-pll and use its clock
accordingly.
Signed-off-by: Chuanhong Guo <[email protected]>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index a4c08110094b..12717f570ceb 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -27,12 +28,11 @@
serial0 = &uartlite;
};
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
+ pll: pll {
+ compatible = "mediatek,mt7621-pll", "syscon";
- /* FIXME: there should be way to detect this */
- clock-frequency = <880000000>;
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "bus";
};
sysclock: sysclock@0 {
@@ -155,7 +155,6 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysclock>;
clock-frequency = <50000000>;
interrupt-parent = <&gic>;
@@ -172,7 +171,7 @@
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&pll MT7621_CLK_BUS>;
resets = <&rstctrl 18>;
reset-names = "spi";
@@ -372,7 +371,7 @@
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&cpuclock>;
+ clocks = <&pll MT7621_CLK_CPU>;
};
};
--
2.21.0
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao <[email protected]>
Signed-off-by: Chuanhong Guo <[email protected]>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 12717f570ceb..ac9189276590 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -138,7 +138,7 @@
memc: memc@5000 {
compatible = "mtk,mt7621-memc";
- reg = <0x300 0x100>;
+ reg = <0x5000 0x1000>;
};
cpc: cpc@1fbf0000 {
--
2.21.0
On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo <[email protected]> wrote:
>
> This commit adds device-tree node for mt7621-pll and use its clock
> accordingly.
>
> Signed-off-by: Chuanhong Guo <[email protected]>
Oops. Please ignore this single patch for now. I forgot to drop
cpuclock node in drivers/staging/mt7621-dts/gbpc1.dts
I'll resend this patch with changes for gbpc1.dts after the other four
patches are applied.
> ---
> drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> index a4c08110094b..12717f570ceb 100644
> --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> @@ -1,4 +1,5 @@
> #include <dt-bindings/interrupt-controller/mips-gic.h>
> +#include <dt-bindings/clock/mt7621-clk.h>
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> @@ -27,12 +28,11 @@
> serial0 = &uartlite;
> };
>
> - cpuclock: cpuclock@0 {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> + pll: pll {
> + compatible = "mediatek,mt7621-pll", "syscon";
>
> - /* FIXME: there should be way to detect this */
> - clock-frequency = <880000000>;
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> };
>
> sysclock: sysclock@0 {
> @@ -155,7 +155,6 @@
> compatible = "ns16550a";
> reg = <0xc00 0x100>;
>
> - clocks = <&sysclock>;
> clock-frequency = <50000000>;
>
> interrupt-parent = <&gic>;
> @@ -172,7 +171,7 @@
> compatible = "ralink,mt7621-spi";
> reg = <0xb00 0x100>;
>
> - clocks = <&sysclock>;
> + clocks = <&pll MT7621_CLK_BUS>;
>
> resets = <&rstctrl 18>;
> reset-names = "spi";
> @@ -372,7 +371,7 @@
> timer {
> compatible = "mti,gic-timer";
> interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> - clocks = <&cpuclock>;
> + clocks = <&pll MT7621_CLK_CPU>;
> };
> };
>
> --
> 2.21.0
>
The subject of this patch is confusing. Not sure what it has to do with
"MIPS:" so maybe remove that and prefix it "dt-bindings: clock:"
instead.
Quoting Chuanhong Guo (2019-07-09 11:20:14)
> This patch adds dt binding header for mediatek,mt7621-pll
>
> Signed-off-by: Weijie Gao <[email protected]>
> Signed-off-by: Chuanhong Guo <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
Otherwise looks ok to me. Should I apply it to clk tree?
> include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
Quoting Chuanhong Guo (2019-07-09 11:20:16)
> This commit adds device tree binding documentation for MT7621
> PLL controller.
>
> Signed-off-by: Chuanhong Guo <[email protected]>
> ---
> .../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> new file mode 100644
> index 000000000000..05c15062cd20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> @@ -0,0 +1,19 @@
> +Binding for Mediatek MT7621 PLL controller
> +
> +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
> +
> +Required Properties:
> +- compatible: has to be "mediatek,mt7621-pll"
> +- #clock-cells: has to be one
> +
> +Optional properties:
> +- clock-output-names: should be "cpu", "bus"
> +
> +Example:
> + pll {
> + compatible = "mediatek,mt7621-pll", "syscon";
Why is this a syscon and not just part of some larger mt7621 clk
provider node?
> +
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> + };
> +