Change MMC0 clock settings and set parent to MOUT_SPLL with proper rate.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 38edb00c7f1b..c8e02ecc6627 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -891,6 +891,9 @@
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
+ assigned-clocks = <&clock CLK_MOUT_MMC0>, <&clock CLK_FOUT_SPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_SPLL>;
+ assigned-clock-rates = <0>, <800000000>;
};
&nocp_mem0_0 {
--
2.17.1