Dear All,
Here are some patches which help tune USB 3.0 phy.
changes have been testing on Odroid XU3 / XU4 / HC1.
with suspend and resume working with usb hdd device connected.
These patches have been build on top on Marek Szyprowski
Fix USB3.0 DRD PHY calibration issues.
[0] https://patchwork.kernel.org/cover/11049823/
Anand Moon (5):
phy: exynos5-usbdrd: read from correct offset of xhci linksystem
phy: exynos5-usbdrd: add missing tuning of the phyutmi signal
phy: exynos5-usbdrd: UTMI tune signal
phy: exynos5-usbdrd: PIPE3 tune signal
phy: exynos5-usbdrd: drop duplicate setting PIPE3 tune signal
drivers/phy/samsung/phy-exynos5-usbdrd.c | 101 ++++++++++++++++++-----
1 file changed, 82 insertions(+), 19 deletions(-)
--
2.22.0
Add missing tuning of phyutmi controls to enter suspend and
resume state.
Signed-off-by: Anand Moon <[email protected]>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 32 ++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 3c14bf7718c1..135114d51bc1 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -42,7 +42,13 @@
#define EXYNOS5_DRD_PHYUTMI 0x08
+#define PHYUTMI_TXBITSTUFFENH BIT(8)
+#define PHYUTMI_TXBITSTUFFEN BIT(7)
#define PHYUTMI_OTGDISABLE BIT(6)
+#define PHYUTMI_IDPULLUP BIT(5)
+#define PHYUTMI_DRVVBUS BIT(4)
+#define PHYUTMI_DPPULLDOWN BIT(3)
+#define PHYUTMI_DMPULLDOWN BIT(2)
#define PHYUTMI_FORCESUSPEND BIT(1)
#define PHYUTMI_FORCESLEEP BIT(0)
@@ -402,6 +408,23 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
LINKSYSTEM_FLADJ(0x20);
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
+ /* High-Byte Transmit Bit-Stuffing Enable */
+ reg |= PHYUTMI_TXBITSTUFFENH;
+ /* Low-Byte Transmit Bit-Stuffing Enable */
+ reg |= PHYUTMI_TXBITSTUFFEN;
+ /* release force_sleep & force_suspend */
+ reg &= ~(PHYUTMI_FORCESLEEP | PHYUTMI_FORCESUSPEND);
+ /* DP/DM Pull Down Disable */
+ reg &= ~(PHYUTMI_DMPULLDOWN | PHYUTMI_DPPULLDOWN);
+ /* drvvbus controller signal controls the VBUS valid comparator */
+ reg &= ~PHYUTMI_OTGDISABLE;
+ /* controller signal controls the VBUS Valid comparator */
+ reg |= PHYUTMI_DRVVBUS;
+ /* Enable ID Sampling */
+ reg |= PHYUTMI_IDPULLUP;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
+
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
/* Select PHY CLK source */
reg &= ~PHYPARAM0_REF_USE_PAD;
@@ -452,9 +475,14 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
if (ret)
return ret;
- reg = PHYUTMI_OTGDISABLE |
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
+ reg |= PHYUTMI_OTGDISABLE |
PHYUTMI_FORCESUSPEND |
- PHYUTMI_FORCESLEEP;
+ PHYUTMI_FORCESLEEP |
+ PHYUTMI_DMPULLDOWN |
+ PHYUTMI_DPPULLDOWN;
+ reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_IDPULLUP |
+ PHYUTMI_TXBITSTUFFENH | PHYUTMI_TXBITSTUFFEN);
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
/* Resetting the PHYCLKRST enable bits to reduce leakage current */
--
2.22.0
Read from linksystem offset to update the xhci version.
Signed-off-by: Anand Moon <[email protected]>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 646259bee909..3c14bf7718c1 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -397,7 +397,8 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
* Setting the Frame length Adj value[6:1] to default 0x20
* See xHCI 1.0 spec, 5.2.4
*/
- reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
+ reg |= LINKSYSTEM_XHCI_VERSION_CONTROL |
LINKSYSTEM_FLADJ(0x20);
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
--
2.22.0
Tune USB2.0 (UTMI+) TX signal for high speed data transfer.
Signed-off-by: Anand Moon <[email protected]>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 42 +++++++++++++++++++++---
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 135114d51bc1..54a513ca15e4 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -33,6 +33,8 @@
#define EXYNOS5_FSEL_24MHZ 0x5
#define EXYNOS5_FSEL_50MHZ 0x7
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
/* EXYNOS5: USB 3.0 DRD PHY registers */
#define EXYNOS5_DRD_LINKSYSTEM 0x04
@@ -108,8 +110,17 @@
#define EXYNOS5_DRD_PHYPARAM0 0x1c
#define PHYPARAM0_REF_USE_PAD BIT(31)
-#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
-#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+#define PHYPARAM0_REF_LOSLEVEL(x) __set(x, 30, 26)
+#define PHYPARAM0_TXVREFTUNE(x) __set(x, 25, 22)
+#define PHYPARAM0_TXISETUNE(x) __set(x, 21, 20)
+#define PHYPARAM0_TXRESTUNE(x) __set(x, 19, 18)
+#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17)
+#define PHYPARAM0_TXPREEMPAMPTUNE(x) __set(x, 16, 15)
+#define PHYPARAM0_TXHSXVTUNE(x) __set(x, 14, 13)
+#define PHYPARAM0_TXFSLSTUNE(x) __set(x, 12, 9)
+#define PHYPARAM0_SQRXTUNE(x) __set(x, 8, 6)
+#define PHYPARAM0_OTGTUNE(x) __set(x, 5, 3)
+#define PHYPARAM0_COMPDISTUNE(x) __set(x, 2, 0)
#define EXYNOS5_DRD_PHYPARAM1 0x20
@@ -365,9 +376,30 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
u32 reg;
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
- /* Set Loss-of-Signal Detector sensitivity */
- reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
- reg |= PHYPARAM0_REF_LOSLEVEL;
+ /* Set Loss-of-Signal Detector sensitivity */
+ reg |= (PHYPARAM0_REF_USE_PAD |
+ /* Sets the sensitivity level for the Loss-of-Signal detector */
+ PHYPARAM0_REF_LOSLEVEL(0x9) |
+ /* Adjusts the high-speed DC level voltage */
+ PHYPARAM0_TXVREFTUNE(0x3) |
+ /* Adjust the rise/fal timie of the high-speed waveform */
+ PHYPARAM0_TXISETUNE(0x1) |
+ /* Adjusts the driver source impedance */
+ PHYPARAM0_TXRESTUNE(0x1) |
+ /* HS Transmitter Pre-Emphasis Duration Control */
+ PHYPARAM0_TXPREEMPPULSETUNE |
+ /* HS Transmitter Pre-Emphasis Current Control */
+ PHYPARAM0_TXPREEMPAMPTUNE(0x0) |
+ /* Transmitter High-Speed Crossover Adjustment */
+ PHYPARAM0_TXHSXVTUNE(0x3) |
+ /* FS/LS Source Impedance Adjustment */
+ PHYPARAM0_TXFSLSTUNE(0x3) |
+ /* Squelch Threshold Adjustment */
+ PHYPARAM0_SQRXTUNE(0x3) |
+ /* VBUS Valid Threshold Adjustment */
+ PHYPARAM0_OTGTUNE(0x6) |
+ /* Disconnect Threshold Adjustment */
+ PHYPARAM0_COMPDISTUNE(0x6));
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
--
2.22.0
Tune USB3.0 (PIPE3) PHY TX signal for high and supper
speed data transfer.
Signed-off-by: Anand Moon <[email protected]>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 54a513ca15e4..4f16c4f82ae5 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -124,8 +124,10 @@
#define EXYNOS5_DRD_PHYPARAM1 0x20
-#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
-#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+#define PHYPARAM1_TX0_TERM_OFFSET(x) __set(x, 30, 26)
+#define PHYPARAM1_TX_SWING_FULL(x) __set(x, 18, 12)
+#define PHYPRAAM1_PCS_TX_DEEMPH_6DB(x) __set(x, 11, 6)
+#define PHYPRAAM1_PCS_TX_DEEMPH_3P5DB(x) __set(x, 5, 0)
#define EXYNOS5_DRD_PHYTERM 0x24
@@ -360,10 +362,16 @@ static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
{
u32 reg;
- reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
/* Set Tx De-Emphasis level */
- reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
- reg |= PHYPARAM1_PCS_TXDEEMPH;
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
+ /* Transmitter Termination Offset */
+ reg |= PHYPARAM1_TX0_TERM_OFFSET(0x5) |
+ /* Tx Amplitude (Full Swing mode) */
+ PHYPARAM1_TX_SWING_FULL(0x3F) |
+ /* Tx De-Emphasis at 6 dB */
+ PHYPRAAM1_PCS_TX_DEEMPH_6DB(0x20) |
+ /* Tx De-Emphasis at 3.5 dB */
+ PHYPRAAM1_PCS_TX_DEEMPH_3P5DB(0x15);
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
--
2.22.0
Drop duplicate configuration setting of PIPE tune signal.
Signed-off-by: Anand Moon <[email protected]>
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 4f16c4f82ae5..f6d2f359d88a 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -410,12 +410,6 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
PHYPARAM0_COMPDISTUNE(0x6));
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
- reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
- /* Set Tx De-Emphasis level */
- reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
- reg |= PHYPARAM1_PCS_TXDEEMPH;
- writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
-
/* UTMI Power Control */
writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
--
2.22.0
On Mon, 22 Jul 2019 at 20:59, Anand Moon <[email protected]> wrote:
>
> Read from linksystem offset to update the xhci version.
But why? As many times before, you do not specify why you are doing
things. What problem are you solving? What feature are you adding?
Best regards,
Krzysztof
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 646259bee909..3c14bf7718c1 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -397,7 +397,8 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
> * Setting the Frame length Adj value[6:1] to default 0x20
> * See xHCI 1.0 spec, 5.2.4
> */
> - reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
> + reg |= LINKSYSTEM_XHCI_VERSION_CONTROL |
> LINKSYSTEM_FLADJ(0x20);
> writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
>
> --
> 2.22.0
>
On Mon, 22 Jul 2019 at 20:59, Anand Moon <[email protected]> wrote:
>
> Add missing tuning of phyutmi controls to enter suspend and
> resume state.
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 32 ++++++++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 3c14bf7718c1..135114d51bc1 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -42,7 +42,13 @@
>
> #define EXYNOS5_DRD_PHYUTMI 0x08
>
> +#define PHYUTMI_TXBITSTUFFENH BIT(8)
> +#define PHYUTMI_TXBITSTUFFEN BIT(7)
> #define PHYUTMI_OTGDISABLE BIT(6)
> +#define PHYUTMI_IDPULLUP BIT(5)
> +#define PHYUTMI_DRVVBUS BIT(4)
> +#define PHYUTMI_DPPULLDOWN BIT(3)
> +#define PHYUTMI_DMPULLDOWN BIT(2)
> #define PHYUTMI_FORCESUSPEND BIT(1)
> #define PHYUTMI_FORCESLEEP BIT(0)
>
> @@ -402,6 +408,23 @@ static int exynos5_usbdrd_phy_init(struct phy *phy)
> LINKSYSTEM_FLADJ(0x20);
> writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
>
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
> + /* High-Byte Transmit Bit-Stuffing Enable */
> + reg |= PHYUTMI_TXBITSTUFFENH;
How this is related with suspend and resume?
> + /* Low-Byte Transmit Bit-Stuffing Enable */
> + reg |= PHYUTMI_TXBITSTUFFEN;
The same.
> + /* release force_sleep & force_suspend */
> + reg &= ~(PHYUTMI_FORCESLEEP | PHYUTMI_FORCESUSPEND);
Really, why?
> + /* DP/DM Pull Down Disable */
> + reg &= ~(PHYUTMI_DMPULLDOWN | PHYUTMI_DPPULLDOWN);
Care to explain why?
> + /* drvvbus controller signal controls the VBUS valid comparator */
> + reg &= ~PHYUTMI_OTGDISABLE;
Makes sense, but how is it connected with suspend and resume? It's the
default, BTW...
> + /* controller signal controls the VBUS Valid comparator */
> + reg |= PHYUTMI_DRVVBUS;
Again, you are setting the defaults...
> + /* Enable ID Sampling */
> + reg |= PHYUTMI_IDPULLUP;
The same...
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
Does not look good. For UTMI Phy, this will be overwritten few lines
later with exynos5_usbdrd_utmi_init().
> +
> reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> /* Select PHY CLK source */
> reg &= ~PHYPARAM0_REF_USE_PAD;
> @@ -452,9 +475,14 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
> if (ret)
> return ret;
>
> - reg = PHYUTMI_OTGDISABLE |
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
> + reg |= PHYUTMI_OTGDISABLE |
> PHYUTMI_FORCESUSPEND |
> - PHYUTMI_FORCESLEEP;
> + PHYUTMI_FORCESLEEP |
> + PHYUTMI_DMPULLDOWN |
> + PHYUTMI_DPPULLDOWN;
> + reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_IDPULLUP |
> + PHYUTMI_TXBITSTUFFENH | PHYUTMI_TXBITSTUFFEN);
No, it looks like random code... why you want to update the register
instead of overwrite it?
Best regards,
Krzysztof
> writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
>
> /* Resetting the PHYCLKRST enable bits to reduce leakage current */
> --
> 2.22.0
>
On Mon, 22 Jul 2019 at 20:59, Anand Moon <[email protected]> wrote:
>
> Tune USB2.0 (UTMI+) TX signal for high speed data transfer.
What is the visible effect? What does this tuning bring?
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 42 +++++++++++++++++++++---
> 1 file changed, 37 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 135114d51bc1..54a513ca15e4 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -33,6 +33,8 @@
> #define EXYNOS5_FSEL_24MHZ 0x5
> #define EXYNOS5_FSEL_50MHZ 0x7
>
> +#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
> +
> /* EXYNOS5: USB 3.0 DRD PHY registers */
> #define EXYNOS5_DRD_LINKSYSTEM 0x04
>
> @@ -108,8 +110,17 @@
> #define EXYNOS5_DRD_PHYPARAM0 0x1c
>
> #define PHYPARAM0_REF_USE_PAD BIT(31)
> -#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
> -#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
> +#define PHYPARAM0_REF_LOSLEVEL(x) __set(x, 30, 26)
> +#define PHYPARAM0_TXVREFTUNE(x) __set(x, 25, 22)
> +#define PHYPARAM0_TXISETUNE(x) __set(x, 21, 20)
> +#define PHYPARAM0_TXRESTUNE(x) __set(x, 19, 18)
> +#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17)
> +#define PHYPARAM0_TXPREEMPAMPTUNE(x) __set(x, 16, 15)
> +#define PHYPARAM0_TXHSXVTUNE(x) __set(x, 14, 13)
> +#define PHYPARAM0_TXFSLSTUNE(x) __set(x, 12, 9)
> +#define PHYPARAM0_SQRXTUNE(x) __set(x, 8, 6)
> +#define PHYPARAM0_OTGTUNE(x) __set(x, 5, 3)
> +#define PHYPARAM0_COMPDISTUNE(x) __set(x, 2, 0)
>
> #define EXYNOS5_DRD_PHYPARAM1 0x20
>
> @@ -365,9 +376,30 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
> u32 reg;
>
> reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> - /* Set Loss-of-Signal Detector sensitivity */
> - reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
> - reg |= PHYPARAM0_REF_LOSLEVEL;
> + /* Set Loss-of-Signal Detector sensitivity */
> + reg |= (PHYPARAM0_REF_USE_PAD |
> + /* Sets the sensitivity level for the Loss-of-Signal detector */
> + PHYPARAM0_REF_LOSLEVEL(0x9) |
> + /* Adjusts the high-speed DC level voltage */
> + PHYPARAM0_TXVREFTUNE(0x3) |
> + /* Adjust the rise/fal timie of the high-speed waveform */
> + PHYPARAM0_TXISETUNE(0x1) |
> + /* Adjusts the driver source impedance */
> + PHYPARAM0_TXRESTUNE(0x1) |
> + /* HS Transmitter Pre-Emphasis Duration Control */
> + PHYPARAM0_TXPREEMPPULSETUNE |
> + /* HS Transmitter Pre-Emphasis Current Control */
> + PHYPARAM0_TXPREEMPAMPTUNE(0x0) |
> + /* Transmitter High-Speed Crossover Adjustment */
> + PHYPARAM0_TXHSXVTUNE(0x3) |
> + /* FS/LS Source Impedance Adjustment */
> + PHYPARAM0_TXFSLSTUNE(0x3) |
> + /* Squelch Threshold Adjustment */
> + PHYPARAM0_SQRXTUNE(0x3) |
> + /* VBUS Valid Threshold Adjustment */
> + PHYPARAM0_OTGTUNE(0x6) |
> + /* Disconnect Threshold Adjustment */
> + PHYPARAM0_COMPDISTUNE(0x6));
You set a bunch of parameters but I am not sure how did you get the values...
Best regards,
Krzysztof
> writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
>
> reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> --
> 2.22.0
>
On Mon, 22 Jul 2019 at 20:59, Anand Moon <[email protected]> wrote:
>
> Tune USB3.0 (PIPE3) PHY TX signal for high and supper
> speed data transfer.
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 54a513ca15e4..4f16c4f82ae5 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -124,8 +124,10 @@
>
> #define EXYNOS5_DRD_PHYPARAM1 0x20
>
> -#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
> -#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
> +#define PHYPARAM1_TX0_TERM_OFFSET(x) __set(x, 30, 26)
> +#define PHYPARAM1_TX_SWING_FULL(x) __set(x, 18, 12)
> +#define PHYPRAAM1_PCS_TX_DEEMPH_6DB(x) __set(x, 11, 6)
> +#define PHYPRAAM1_PCS_TX_DEEMPH_3P5DB(x) __set(x, 5, 0)
>
> #define EXYNOS5_DRD_PHYTERM 0x24
>
> @@ -360,10 +362,16 @@ static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
> {
> u32 reg;
>
> - reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> /* Set Tx De-Emphasis level */
> - reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
> - reg |= PHYPARAM1_PCS_TXDEEMPH;
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> + /* Transmitter Termination Offset */
> + reg |= PHYPARAM1_TX0_TERM_OFFSET(0x5) |
> + /* Tx Amplitude (Full Swing mode) */
> + PHYPARAM1_TX_SWING_FULL(0x3F) |
> + /* Tx De-Emphasis at 6 dB */
> + PHYPRAAM1_PCS_TX_DEEMPH_6DB(0x20) |
> + /* Tx De-Emphasis at 3.5 dB */
> + PHYPRAAM1_PCS_TX_DEEMPH_3P5DB(0x15);
How did you get the value? Why you are changing existing values to default ones?
Best regards,
Krzysztof
> writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
>
> reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> --
> 2.22.0
>
On Mon, 22 Jul 2019 at 21:00, Anand Moon <[email protected]> wrote:
>
> Drop duplicate configuration setting of PIPE tune signal.
There is no duplicate set. This is either completely wrong or put in
wrong order of entire patchset...
Best regards,
Krzysztof