This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
the MTP for SM8150.
Changes in v2:
- Squash patches
- Fix comments given by Stephen namely, lowercase for hext numbers,
making rpmhcc have xo_board as parent, rename pon controller to
power-on controller, make pmic nodes as disabled etc.
- removed the dependency on clk defines and use raw numbers
Vinod Koul (8):
arm64: dts: qcom: sm8150: add base dts file
arm64: dts: qcom: pm8150: Add Base DTS file
arm64: dts: qcom: pm8150b: Add Base DTS file
arm64: dts: qcom: pm8150l: Add Base DTS file
arm64: dts: qcom: sm8150-mtp: add base dts file
arm64: dts: qcom: sm8150-mtp: Add regulators
arm64: dts: qcom: sm8150: Add reserved-memory regions
arm64: dts: qcom: sm8150: Add apps shared nodes
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/pm8150.dtsi | 95 +++++
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 84 +++++
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 78 ++++
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 375 +++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 479 ++++++++++++++++++++++++
6 files changed, 1112 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pm8150b.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pm8150l.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/sm8150-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
--
2.20.1
Add base DTS file for pm8150 along with GPIOs, power-on, rtc and vadc
nodes
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 95 ++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
new file mode 100644
index 000000000000..4a678be46d37
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+// Copyright (c) 2019, Linaro Limited
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pm8150_0: pmic@0 {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon: power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+
+ status = "disabled";
+ };
+ };
+
+ pm8150_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+
+ status = "disabled";
+ };
+
+ pm8150_gpios: gpio@c000 {
+ compatible = "qcom,pm8150-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+ <0 0xc1 0 IRQ_TYPE_NONE>,
+ <0 0xc2 0 IRQ_TYPE_NONE>,
+ <0 0xc3 0 IRQ_TYPE_NONE>,
+ <0 0xc4 0 IRQ_TYPE_NONE>,
+ <0 0xc5 0 IRQ_TYPE_NONE>,
+ <0 0xc6 0 IRQ_TYPE_NONE>,
+ <0 0xc7 0 IRQ_TYPE_NONE>,
+ <0 0xc8 0 IRQ_TYPE_NONE>,
+ <0 0xc9 0 IRQ_TYPE_NONE>,
+ <0 0xca 0 IRQ_TYPE_NONE>,
+ <0 0xcb 0 IRQ_TYPE_NONE>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
--
2.20.1
PMIC pm8150b is a slave pmic and this adds base DTS file for pm8150b
with pon, adc, and gpio nodes
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 84 +++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150b.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
new file mode 100644
index 000000000000..dfb71fb8c90a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+// Copyright (c) 2019, Linaro Limited
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@2 {
+ compatible = "qcom,pm8150b", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+
+ status = "disabled";
+ };
+
+ adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+
+ chg-temp@9 {
+ reg = <ADC5_CHG_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "chg_temp";
+ };
+ };
+
+ pm8150b_gpios: gpio@c000 {
+ compatible = "qcom,pm8150b-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>,
+ <0x2 0xc1 0 IRQ_TYPE_NONE>,
+ <0x2 0xc2 0 IRQ_TYPE_NONE>,
+ <0x2 0xc3 0 IRQ_TYPE_NONE>,
+ <0x2 0xc4 0 IRQ_TYPE_NONE>,
+ <0x2 0xc5 0 IRQ_TYPE_NONE>,
+ <0x2 0xc6 0 IRQ_TYPE_NONE>,
+ <0x2 0xc7 0 IRQ_TYPE_NONE>,
+ <0x2 0xc8 0 IRQ_TYPE_NONE>,
+ <0x2 0xc9 0 IRQ_TYPE_NONE>,
+ <0x2 0xca 0 IRQ_TYPE_NONE>,
+ <0x2 0xcb 0 IRQ_TYPE_NONE>;
+ };
+ };
+
+ pmic@3 {
+ compatible = "qcom,pm8150b", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
--
2.20.1
This add base DTS file with cpu, psci, firmware, clock, tlmm and
spmi nodes which enables boot to console
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++++++++++++++++++++++++++
1 file changed, 305 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
new file mode 100644
index 000000000000..d9dc95f851b7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+// Copyright (c) 2019, Linaro Limited
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo485";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm8150", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sm8150";
+ reg = <0x00100000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo",
+ "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ };
+
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x00ac0000 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc 123>,
+ <&gcc 124>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ uart2: serial@a90000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x00a90000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc 105>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ tlmm: pinctrl@3100000 {
+ compatible = "qcom,sm8150-pinctrl";
+ reg = <0x03100000 0x300000>,
+ <0x03500000 0x300000>,
+ <0x03900000 0x300000>,
+ <0x03d00000 0x300000>;
+ reg-names = "west", "east", "north", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&tlmm 0 0 175>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17a60000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17c20000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000{
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c26000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0c440000 0x0001100>,
+ <0x0c600000 0x2000000>,
+ <0x0e600000 0x0100000>,
+ <0x0e700000 0x00a0000>,
+ <0x0c40a000 0x0026000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.20.1
This add base DTS file for sm8150-mtp and enables boot to console, adds
tlmm reserved range, resin node, volume down key and also includes pmic
file.
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 48 +++++++++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8150-mtp.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 0a7e5dfce6f7..1964dacaf19b 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -12,5 +12,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
new file mode 100644
index 000000000000..80b15f4f07c8
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+// Copyright (c) 2019, Linaro Limited
+
+/dts-v1/;
+
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8150 MTP";
+ compatible = "qcom,sm8150-mtp";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&pon {
+ pwrkey {
+ status = "okay";
+ };
+
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+};
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <126 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.20.1
PMIC pm8150l is a slave pmic and this adds base DTS file for pm8150l
with power-on, adc and gpio nodes
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 78 +++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150l.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
new file mode 100644
index 000000000000..5022ac3fd9b7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+// Copyright (c) 2019, Linaro Limited
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@4 {
+ compatible = "qcom,pm8150l", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+
+ status = "disabled";
+ };
+
+ adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pm8150l_gpios: gpio@c000 {
+ compatible = "qcom,pm8150l-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>,
+ <0x4 0xc1 0 IRQ_TYPE_NONE>,
+ <0x4 0xc2 0 IRQ_TYPE_NONE>,
+ <0x4 0xc3 0 IRQ_TYPE_NONE>,
+ <0x4 0xc4 0 IRQ_TYPE_NONE>,
+ <0x4 0xc5 0 IRQ_TYPE_NONE>,
+ <0x4 0xc6 0 IRQ_TYPE_NONE>,
+ <0x4 0xc7 0 IRQ_TYPE_NONE>,
+ <0x4 0xc8 0 IRQ_TYPE_NONE>,
+ <0x4 0xc9 0 IRQ_TYPE_NONE>,
+ <0x4 0xca 0 IRQ_TYPE_NONE>,
+ <0x4 0xcb 0 IRQ_TYPE_NONE>;
+ };
+ };
+
+ pmic@5 {
+ compatible = "qcom,pm8150l", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
--
2.20.1
Add the reserved memory regions in SM8150
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 111 +++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index d9dc95f851b7..8bf4b4c17ae0 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -153,6 +153,117 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@85700000 {
+ reg = <0x0 0x85700000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@85d00000 {
+ reg = <0x0 0x85d00000 0x0 0x140000>;
+ no-map;
+ };
+
+ aop_mem: memory@85f00000 {
+ reg = <0x0 0x85f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_cmd_db: memory@85f20000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x85f20000 0x0 0x20000>;
+ no-map;
+ };
+
+ smem_mem: memory@86000000 {
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+ };
+
+ tz_mem: memory@86200000 {
+ reg = <0x0 0x86200000 0x0 0x3900000>;
+ no-map;
+ };
+
+ rmtfs_mem: memory@89b00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x89b00000 0x0 0x200000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
+
+ camera_mem: memory@8b700000 {
+ reg = <0x0 0x8b700000 0x0 0x500000>;
+ no-map;
+ };
+
+ wlan_mem: memory@8bc00000 {
+ reg = <0x0 0x8bc00000 0x0 0x180000>;
+ no-map;
+ };
+
+ npu_mem: memory@8bd80000 {
+ reg = <0x0 0x8bd80000 0x0 0x80000>;
+ no-map;
+ };
+
+ adsp_mem: memory@8be00000 {
+ reg = <0x0 0x8be00000 0x0 0x1a00000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8d800000 {
+ reg = <0x0 0x8d800000 0x0 0x9600000>;
+ no-map;
+ };
+
+ venus_mem: memory@96e00000 {
+ reg = <0x0 0x96e00000 0x0 0x500000>;
+ no-map;
+ };
+
+ slpi_mem: memory@97300000 {
+ reg = <0x0 0x97300000 0x0 0x1400000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@98700000 {
+ reg = <0x0 0x98700000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@98710000 {
+ reg = <0x0 0x98710000 0x0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: memory@98715000 {
+ reg = <0x0 0x98715000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: memory@98800000 {
+ reg = <0x0 0x98800000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: memory@98900000 {
+ reg = <0x0 0x98900000 0x0 0x1400000>;
+ no-map;
+ };
+
+ qseecom_mem: memory@9e400000 {
+ reg = <0 0x9e400000 0 0x1400000>;
+ no-map;
+ };
+ };
+
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
--
2.20.1
Add the regulators found in the mtp platform. This platform consists of
pmic PM8150, PM8150L and PM8009.
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 327 ++++++++++++++++++++++++
1 file changed, 327 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
index 80b15f4f07c8..0513b24496f6 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -4,6 +4,7 @@
/dts-v1/;
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8150.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -20,6 +21,332 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s5a_2p0: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vdda_wcss_pll:
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_pdphy:
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_csi_0_0p9:
+ vdda_csi_1_0p9:
+ vdda_csi_2_0p9:
+ vdda_csi_3_0p9:
+ vdda_dsi_0_0p9:
+ vdda_dsi_1_0p9:
+ vdda_dsi_0_pll_0p9:
+ vdda_dsi_1_pll_0p9:
+ vdda_pcie_1ln_core:
+ vdda_pcie_2ln_core:
+ vdda_pll_hv_cc_ebi01:
+ vdda_pll_hv_cc_ebi23:
+ vdda_qrefs_0p875_5:
+ vdda_sp_sensor:
+ vdda_ufs_2ln_core_1:
+ vdda_ufs_2ln_core_2:
+ vdda_usb_ss_dp_core_1:
+ vdda_usb_ss_dp_core_2:
+ vdda_qlink_lv:
+ vdda_qlink_lv_ck:
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_10:
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_qfprom:
+ vdd_qfprom_sp:
+ vdda_apc_cs_1p8:
+ vdda_gfx_cs_1p8:
+ vdda_usb_hs_1p8:
+ vdda_qrefs_vref_1p8:
+ vddpx_10_a:
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_wcss_adcdac_1:
+ vdda_wcss_adcdac_22:
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_hv_ebi0:
+ vdda_hv_ebi1:
+ vdda_hv_ebi2:
+ vdda_hv_ebi3:
+ vdda_hv_refgen0:
+ vdda_qlink_hv_ck:
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_5:
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_6:
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_2:
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+
+ vdd-l2-supply = <&vreg_s8c_1p3>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f_2p85: ldo5 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p85: ldo6 {
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <2856000>;
+ };
+ };
+
};
&qupv3_id_1 {
--
2.20.1
Add apss_shared and apps_rsc including the rpmhcc child node, pmu, SMEM
nodes
Co-developed-by: Sibi Sankar <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 63 ++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8bf4b4c17ae0..cf58b367df28 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -142,12 +142,23 @@
};
};
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -264,6 +275,12 @@
};
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -303,6 +320,11 @@
};
};
+ tcsr_mutex_regs: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x01f40000 0x40000>;
+ };
+
tlmm: pinctrl@3100000 {
compatible = "qcom,sm8150-pinctrl";
reg = <0x03100000 0x300000>,
@@ -318,6 +340,16 @@
#interrupt-cells = <2>;
};
+ aoss_qmp: power-controller@c300000 {
+ compatible = "qcom,sm8150-aoss-qmp";
+ reg = <0x0c300000 0x100000>;
+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apss_shared 0>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
@@ -327,6 +359,12 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ apss_shared: mailbox@17c00000 {
+ compatible = "qcom,sm8150-apss-shared";
+ reg = <0x17c00000 0x1000>;
+ #mbox-cells = <1>;
+ };
+
timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -386,6 +424,31 @@
};
};
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8150-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+ };
+
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0c440000 0x0001100>,
--
2.20.1
On Tue, Aug 20, 2019 at 12:12:15PM +0530, Vinod Koul wrote:
> Add the reserved memory regions in SM8150
Is there a reason not to squash this this patch 1/8 ?
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 111 +++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index d9dc95f851b7..8bf4b4c17ae0 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -153,6 +153,117 @@
> method = "smc";
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hyp_mem: memory@85700000 {
> + reg = <0x0 0x85700000 0x0 0x600000>;
> + no-map;
> + };
> +
> + xbl_mem: memory@85d00000 {
> + reg = <0x0 0x85d00000 0x0 0x140000>;
> + no-map;
> + };
> +
> + aop_mem: memory@85f00000 {
> + reg = <0x0 0x85f00000 0x0 0x20000>;
> + no-map;
> + };
> +
> + aop_cmd_db: memory@85f20000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x85f20000 0x0 0x20000>;
> + no-map;
> + };
> +
> + smem_mem: memory@86000000 {
> + reg = <0x0 0x86000000 0x0 0x200000>;
> + no-map;
> + };
> +
> + tz_mem: memory@86200000 {
> + reg = <0x0 0x86200000 0x0 0x3900000>;
> + no-map;
> + };
> +
> + rmtfs_mem: memory@89b00000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0x0 0x89b00000 0x0 0x200000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + qcom,vmid = <15>;
> + };
> +
> + camera_mem: memory@8b700000 {
> + reg = <0x0 0x8b700000 0x0 0x500000>;
> + no-map;
> + };
> +
> + wlan_mem: memory@8bc00000 {
> + reg = <0x0 0x8bc00000 0x0 0x180000>;
> + no-map;
> + };
> +
> + npu_mem: memory@8bd80000 {
> + reg = <0x0 0x8bd80000 0x0 0x80000>;
> + no-map;
> + };
> +
> + adsp_mem: memory@8be00000 {
> + reg = <0x0 0x8be00000 0x0 0x1a00000>;
> + no-map;
> + };
> +
> + mpss_mem: memory@8d800000 {
> + reg = <0x0 0x8d800000 0x0 0x9600000>;
> + no-map;
> + };
> +
> + venus_mem: memory@96e00000 {
> + reg = <0x0 0x96e00000 0x0 0x500000>;
> + no-map;
> + };
> +
> + slpi_mem: memory@97300000 {
> + reg = <0x0 0x97300000 0x0 0x1400000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: memory@98700000 {
> + reg = <0x0 0x98700000 0x0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: memory@98710000 {
> + reg = <0x0 0x98710000 0x0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: memory@98715000 {
> + reg = <0x0 0x98715000 0x0 0x2000>;
> + no-map;
> + };
> +
> + spss_mem: memory@98800000 {
> + reg = <0x0 0x98800000 0x0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: memory@98900000 {
> + reg = <0x0 0x98900000 0x0 0x1400000>;
> + no-map;
> + };
> +
> + qseecom_mem: memory@9e400000 {
> + reg = <0 0x9e400000 0 0x1400000>;
> + no-map;
> + };
> + };
> +
> soc: soc@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:13PM +0530, Vinod Koul wrote:
> This add base DTS file for sm8150-mtp and enables boot to console, adds
> tlmm reserved range, resin node, volume down key and also includes pmic
> file.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 48 +++++++++++++++++++++++++
> 2 files changed, 49 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-mtp.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 0a7e5dfce6f7..1964dacaf19b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -12,5 +12,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> new file mode 100644
> index 000000000000..80b15f4f07c8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
> +
> +/dts-v1/;
> +
> +#include "sm8150.dtsi"
> +#include "pm8150.dtsi"
> +#include "pm8150b.dtsi"
> +#include "pm8150l.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8150 MTP";
> + compatible = "qcom,sm8150-mtp";
> +
> + aliases {
> + serial0 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&pon {
> + pwrkey {
> + status = "okay";
> + };
> +
> + resin {
> + compatible = "qcom,pm8941-resin";
> + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> + debounce = <15625>;
> + bias-pull-up;
> + linux,code = <KEY_VOLUMEDOWN>;
> + };
> +};
Missing a newline here.
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <126 4>;
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:14PM +0530, Vinod Koul wrote:
> Add the regulators found in the mtp platform. This platform consists of
> pmic PM8150, PM8150L and PM8009.
Is there a reason not to squash this this patch 5/8 ?
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 327 ++++++++++++++++++++++++
> 1 file changed, 327 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> index 80b15f4f07c8..0513b24496f6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> @@ -4,6 +4,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include "sm8150.dtsi"
> #include "pm8150.dtsi"
> #include "pm8150b.dtsi"
> @@ -20,6 +21,332 @@
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + /*
> + * Apparently RPMh does not provide support for PM8150 S4 because it
> + * is always-on; model it as a fixed regulator.
> + */
> + vreg_s4a_1p8: pm8150-s4 {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s4a_1p8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vph_pwr>;
> + };
> +};
> +
> +&apps_rsc {
> + pm8150-rpmh-regulators {
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> + vdd-s9-supply = <&vph_pwr>;
> + vdd-s10-supply = <&vph_pwr>;
> +
> + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
> + vdd-l2-l10-supply = <&vreg_bob>;
> + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
> + vdd-l6-l9-supply = <&vreg_s8c_1p3>;
> + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
> + vdd-l13-l16-l17-supply = <&vreg_bob>;
> +
> + vreg_s5a_2p0: smps5 {
> + regulator-min-microvolt = <1904000>;
> + regulator-max-microvolt = <2000000>;
> + };
> +
> + vreg_s6a_0p9: smps6 {
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <1128000>;
> + };
> +
> + vdda_wcss_pll:
> + vreg_l1a_0p75: ldo1 {
> + regulator-min-microvolt = <752000>;
> + regulator-max-microvolt = <752000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_pdphy:
> + vdda_usb_hs_3p1:
> + vreg_l2a_3p1: ldo2 {
> + regulator-min-microvolt = <3072000>;
> + regulator-max-microvolt = <3072000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l3a_0p8: ldo3 {
> + regulator-min-microvolt = <480000>;
> + regulator-max-microvolt = <932000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_usb_hs_core:
> + vdda_csi_0_0p9:
> + vdda_csi_1_0p9:
> + vdda_csi_2_0p9:
> + vdda_csi_3_0p9:
> + vdda_dsi_0_0p9:
> + vdda_dsi_1_0p9:
> + vdda_dsi_0_pll_0p9:
> + vdda_dsi_1_pll_0p9:
> + vdda_pcie_1ln_core:
> + vdda_pcie_2ln_core:
> + vdda_pll_hv_cc_ebi01:
> + vdda_pll_hv_cc_ebi23:
> + vdda_qrefs_0p875_5:
> + vdda_sp_sensor:
> + vdda_ufs_2ln_core_1:
> + vdda_ufs_2ln_core_2:
> + vdda_usb_ss_dp_core_1:
> + vdda_usb_ss_dp_core_2:
> + vdda_qlink_lv:
> + vdda_qlink_lv_ck:
> + vreg_l5a_0p875: ldo5 {
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6a_1p2: ldo6 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7a_1p8: ldo7 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_10:
> + vreg_l9a_1p2: ldo9 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> +
> + vreg_l10a_2p5: ldo10 {
> + regulator-min-microvolt = <2504000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l11a_0p8: ldo11 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdd_qfprom:
> + vdd_qfprom_sp:
> + vdda_apc_cs_1p8:
> + vdda_gfx_cs_1p8:
> + vdda_usb_hs_1p8:
> + vdda_qrefs_vref_1p8:
> + vddpx_10_a:
> + vreg_l12a_1p8: ldo12 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l13a_2p7: ldo13 {
> + regulator-min-microvolt = <2704000>;
> + regulator-max-microvolt = <2704000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1880000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l15a_1p7: ldo15 {
> + regulator-min-microvolt = <1704000>;
> + regulator-max-microvolt = <1704000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l16a_2p7: ldo16 {
> + regulator-min-microvolt = <2704000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l17a_3p0: ldo17 {
> + regulator-min-microvolt = <2856000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + pm8150l-rpmh-regulators {
> + compatible = "qcom,pm8150l-rpmh-regulators";
> + qcom,pmic-id = "c";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> + vdd-s7-supply = <&vph_pwr>;
> + vdd-s8-supply = <&vph_pwr>;
> +
> + vdd-l1-l8-supply = <&vreg_s4a_1p8>;
> + vdd-l2-l3-supply = <&vreg_s8c_1p3>;
> + vdd-l4-l5-l6-supply = <&vreg_bob>;
> + vdd-l7-l11-supply = <&vreg_bob>;
> + vdd-l9-l10-supply = <&vreg_bob>;
> +
> + vdd-bob-supply = <&vph_pwr>;
> + vdd-flash-supply = <&vreg_bob>;
> + vdd-rgb-supply = <&vreg_bob>;
> +
> + vreg_bob: bob {
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <4000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
> + regulator-allow-bypass;
> + };
> +
> + vreg_s8c_1p3: smps8 {
> + regulator-min-microvolt = <1352000>;
> + regulator-max-microvolt = <1352000>;
> + };
> +
> + vreg_l1c_1p8: ldo1 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdda_wcss_adcdac_1:
> + vdda_wcss_adcdac_22:
> + vreg_l2c_1p3: ldo2 {
> + regulator-min-microvolt = <1304000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vdda_hv_ebi0:
> + vdda_hv_ebi1:
> + vdda_hv_ebi2:
> + vdda_hv_ebi3:
> + vdda_hv_refgen0:
> + vdda_qlink_hv_ck:
> + vreg_l3c_1p2: ldo3 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_5:
> + vreg_l4c_1p8: ldo4 {
> + regulator-min-microvolt = <1704000>;
> + regulator-max-microvolt = <2928000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_6:
> + vreg_l5c_1p8: ldo5 {
> + regulator-min-microvolt = <1704000>;
> + regulator-max-microvolt = <2928000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vddpx_2:
> + vreg_l6c_2p9: ldo6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7c_3p0: ldo7 {
> + regulator-min-microvolt = <2856000>;
> + regulator-max-microvolt = <3104000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l8c_1p8: ldo8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l9c_2p9: ldo9 {
> + regulator-min-microvolt = <2704000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> +
> + vreg_l10c_3p3: ldo10 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l11c_3p3: ldo11 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> + };
> +
> + pm8009-rpmh-regulators {
> + compatible = "qcom,pm8009-rpmh-regulators";
> + qcom,pmic-id = "f";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vreg_bob>;
> +
> + vdd-l2-supply = <&vreg_s8c_1p3>;
> + vdd-l5-l6-supply = <&vreg_bob>;
> +
> + vreg_l2f_1p2: ldo2 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l5f_2p85: ldo5 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l6f_2p85: ldo6 {
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + regulator-min-microvolt = <2856000>;
> + regulator-max-microvolt = <2856000>;
> + };
> + };
> +
> };
>
> &qupv3_id_1 {
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:11PM +0530, Vinod Koul wrote:
> PMIC pm8150b is a slave pmic and this adds base DTS file for pm8150b
> with pon, adc, and gpio nodes
All of your other commit messages refers to it as power-on
instead of pon, be consistent.
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/pm8150b.dtsi | 84 +++++++++++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8150b.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
> new file mode 100644
> index 000000000000..dfb71fb8c90a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
> +
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +
> +&spmi_bus {
> + pmic@2 {
> + compatible = "qcom,pm8150b", "qcom,spmi-pmic";
> + reg = <0x2 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-on@800 {
> + compatible = "qcom,pm8916-pon";
> + reg = <0x0800>;
> +
> + status = "disabled";
> + };
> +
> + adc@3100 {
> + compatible = "qcom,spmi-adc5";
> + reg = <0x3100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> +
> + status = "disabled";
> +
> + ref-gnd@0 {
> + reg = <ADC5_REF_GND>;
> + qcom,pre-scaling = <1 1>;
> + label = "ref_gnd";
> + };
> +
> + vref-1p25@1 {
> + reg = <ADC5_1P25VREF>;
> + qcom,pre-scaling = <1 1>;
> + label = "vref_1p25";
> + };
> +
> + die-temp@6 {
> + reg = <ADC5_DIE_TEMP>;
> + qcom,pre-scaling = <1 1>;
> + label = "die_temp";
> + };
> +
> + chg-temp@9 {
> + reg = <ADC5_CHG_TEMP>;
> + qcom,pre-scaling = <1 1>;
> + label = "chg_temp";
> + };
> + };
> +
> + pm8150b_gpios: gpio@c000 {
> + compatible = "qcom,pm8150b-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>,
> + <0x2 0xc1 0 IRQ_TYPE_NONE>,
> + <0x2 0xc2 0 IRQ_TYPE_NONE>,
> + <0x2 0xc3 0 IRQ_TYPE_NONE>,
> + <0x2 0xc4 0 IRQ_TYPE_NONE>,
> + <0x2 0xc5 0 IRQ_TYPE_NONE>,
> + <0x2 0xc6 0 IRQ_TYPE_NONE>,
> + <0x2 0xc7 0 IRQ_TYPE_NONE>,
> + <0x2 0xc8 0 IRQ_TYPE_NONE>,
> + <0x2 0xc9 0 IRQ_TYPE_NONE>,
> + <0x2 0xca 0 IRQ_TYPE_NONE>,
> + <0x2 0xcb 0 IRQ_TYPE_NONE>;
> + };
> + };
> +
> + pmic@3 {
> + compatible = "qcom,pm8150b", "qcom,spmi-pmic";
> + reg = <0x3 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +};
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:10PM +0530, Vinod Koul wrote:
> Add base DTS file for pm8150 along with GPIOs, power-on, rtc and vadc
> nodes
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/pm8150.dtsi | 95 ++++++++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> new file mode 100644
> index 000000000000..4a678be46d37
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/spmi/spmi.h>
> +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> +
> +&spmi_bus {
> + pm8150_0: pmic@0 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x0 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pon: power-on@800 {
> + compatible = "qcom,pm8916-pon";
> + reg = <0x0800>;
> + pwrkey {
> + compatible = "qcom,pm8941-pwrkey";
> + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
Here you use 0 for 3rd cell
> + debounce = <15625>;
> + bias-pull-up;
> + linux,code = <KEY_POWER>;
> +
> + status = "disabled";
> + };
> + };
> +
> + pm8150_adc: adc@3100 {
> + compatible = "qcom,spmi-adc5";
> + reg = <0x3100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
Here you use 0x0 for 3rd cell, be consistent.
> +
> + status = "disabled";
> +
> + ref-gnd@0 {
> + reg = <ADC5_REF_GND>;
> + qcom,pre-scaling = <1 1>;
> + label = "ref_gnd";
> + };
> +
> + vref-1p25@1 {
> + reg = <ADC5_1P25VREF>;
> + qcom,pre-scaling = <1 1>;
> + label = "vref_1p25";
> + };
> +
> + die-temp@6 {
> + reg = <ADC5_DIE_TEMP>;
> + qcom,pre-scaling = <1 1>;
> + label = "die_temp";
> + };
> + };
> +
> + rtc@6000 {
> + compatible = "qcom,pm8941-rtc";
> + reg = <0x6000>;
> + reg-names = "rtc", "alarm";
> + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> +
> + status = "disabled";
> + };
> +
> + pm8150_gpios: gpio@c000 {
> + compatible = "qcom,pm8150-gpio";
> + reg = <0xc000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
> + <0 0xc1 0 IRQ_TYPE_NONE>,
> + <0 0xc2 0 IRQ_TYPE_NONE>,
> + <0 0xc3 0 IRQ_TYPE_NONE>,
> + <0 0xc4 0 IRQ_TYPE_NONE>,
> + <0 0xc5 0 IRQ_TYPE_NONE>,
> + <0 0xc6 0 IRQ_TYPE_NONE>,
> + <0 0xc7 0 IRQ_TYPE_NONE>,
> + <0 0xc8 0 IRQ_TYPE_NONE>,
> + <0 0xc9 0 IRQ_TYPE_NONE>,
> + <0 0xca 0 IRQ_TYPE_NONE>,
> + <0 0xcb 0 IRQ_TYPE_NONE>;
> + };
> + };
> +
> + pmic@1 {
> + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> + reg = <0x1 SPMI_USID>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +};
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:09PM +0530, Vinod Koul wrote:
> This add base DTS file with cpu, psci, firmware, clock, tlmm and
> spmi nodes which enables boot to console
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++++++++++++++++++++++++++
> 1 file changed, 305 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> new file mode 100644
> index 000000000000..d9dc95f851b7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
What is the point of an empty node without a label?
Perhaps I'm missing something.
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <38400000>;
> + clock-output-names = "xo_board";
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + clock-output-names = "sleep_clk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
I don't see this compatible in
Documentation/devicetree/bindings/arm/cpus.yaml
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> +
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> + };
I was expecting to see the cpu-map here, defining
the core to cluster relationship.
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm8150", "qcom,scm";
> + #reset-cells = <1>;
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sm8150";
> + reg = <0x00100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clock-names = "bi_tcxo",
> + "sleep_clk";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>;
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x00ac0000 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc 123>,
> + <&gcc 124>;
Is there no defines for these?
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + uart2: serial@a90000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x00a90000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc 105>;
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3100000 {
> + compatible = "qcom,sm8150-pinctrl";
> + reg = <0x03100000 0x300000>,
> + <0x03500000 0x300000>,
> + <0x03900000 0x300000>,
> + <0x03d00000 0x300000>;
> + reg-names = "west", "east", "north", "south";
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-ranges = <&tlmm 0 0 175>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x17a00000 0x10000>, /* GICD */
> + <0x17a60000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer@17c20000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x17c20000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@17c21000{
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c21000 0x1000>,
> + <0x17c22000 0x1000>;
> + };
> +
> + frame@17c23000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c23000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c25000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c25000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c27000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c26000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c29000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c29000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2d000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0c440000 0x0001100>,
> + <0x0c600000 0x2000000>,
> + <0x0e600000 0x0100000>,
> + <0x0e700000 0x00a0000>,
> + <0x0c40a000 0x0026000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + cell-index = <0>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> --
> 2.20.1
>
On Tue, Aug 20, 2019 at 12:12:08PM +0530, Vinod Koul wrote:
> This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
> the MTP for SM8150.
>
> Changes in v2:
> - Squash patches
> - Fix comments given by Stephen namely, lowercase for hext numbers,
> making rpmhcc have xo_board as parent, rename pon controller to
> power-on controller, make pmic nodes as disabled etc.
> - removed the dependency on clk defines and use raw numbers
>
> Vinod Koul (8):
> arm64: dts: qcom: sm8150: add base dts file
> arm64: dts: qcom: pm8150: Add Base DTS file
> arm64: dts: qcom: pm8150b: Add Base DTS file
> arm64: dts: qcom: pm8150l: Add Base DTS file
> arm64: dts: qcom: sm8150-mtp: add base dts file
Use consistent naming.
> arm64: dts: qcom: sm8150-mtp: Add regulators
> arm64: dts: qcom: sm8150: Add reserved-memory regions
> arm64: dts: qcom: sm8150: Add apps shared nodes
>
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/pm8150.dtsi | 95 +++++
> arch/arm64/boot/dts/qcom/pm8150b.dtsi | 84 +++++
> arch/arm64/boot/dts/qcom/pm8150l.dtsi | 78 ++++
> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 375 +++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 479 ++++++++++++++++++++++++
> 6 files changed, 1112 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/pm8150b.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/pm8150l.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
>
> --
> 2.20.1
>
On 20-08-19, 14:27, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:09PM +0530, Vinod Koul wrote:
> > This add base DTS file with cpu, psci, firmware, clock, tlmm and
> > spmi nodes which enables boot to console
> >
> > Signed-off-by: Vinod Koul <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++++++++++++++++++++++++++
> > 1 file changed, 305 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > new file mode 100644
> > index 000000000000..d9dc95f851b7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> > +// Copyright (c) 2019, Linaro Limited
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > +#include <dt-bindings/clock/qcom,rpmh.h>
> > +
> > +/ {
> > + interrupt-parent = <&intc>;
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + chosen { };
>
> What is the point of an empty node without a label?
> Perhaps I'm missing something.
Hmm that seems to be the case with other dts in qcom folder :), we do
have chosen in mtp dts as well which is not empty
>
> > +
> > + clocks {
> > + xo_board: xo-board {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <38400000>;
> > + clock-output-names = "xo_board";
> > + };
> > +
> > + sleep_clk: sleep-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32764>;
> > + clock-output-names = "sleep_clk";
> > + };
> > + };
> > +
> > + cpus {
> > + #address-cells = <2>;
> > + #size-cells = <0>;
> > +
> > + CPU0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
>
> I don't see this compatible in
> Documentation/devicetree/bindings/arm/cpus.yaml
Thanks for pointing, will send
>
> > + reg = <0x0 0x0>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + L2_0: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + L3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > + };
> > +
> > + CPU1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x100>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_100>;
> > + L2_100: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > +
> > + };
> > +
> > + CPU2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x200>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_200>;
> > + L2_200: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x300>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_300>;
> > + L2_300: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU4: cpu@400 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x400>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_400>;
> > + L2_400: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU5: cpu@500 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x500>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_500>;
> > + L2_500: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU6: cpu@600 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x600>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_600>;
> > + L2_600: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU7: cpu@700 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo485";
> > + reg = <0x0 0x700>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_700>;
> > + L2_700: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > + };
>
> I was expecting to see the cpu-map here, defining
> the core to cluster relationship.
That would come later with bunch of other support
>
> > +
> > + firmware {
> > + scm: scm {
> > + compatible = "qcom,scm-sm8150", "qcom,scm";
> > + #reset-cells = <1>;
> > + };
> > + };
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + /* We expect the bootloader to fill in the size */
> > + reg = <0 0x80000000 0 0>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + soc: soc@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0 0 0xffffffff>;
> > + compatible = "simple-bus";
> > +
> > + gcc: clock-controller@100000 {
> > + compatible = "qcom,gcc-sm8150";
> > + reg = <0x00100000 0x1f0000>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <1>;
> > + clock-names = "bi_tcxo",
> > + "sleep_clk";
> > + clocks = <&rpmhcc RPMH_CXO_CLK>,
> > + <&sleep_clk>;
> > + };
> > +
> > + qupv3_id_1: geniqup@ac0000 {
> > + compatible = "qcom,geni-se-qup";
> > + reg = <0x00ac0000 0x6000>;
> > + clock-names = "m-ahb", "s-ahb";
> > + clocks = <&gcc 123>,
> > + <&gcc 124>;
>
> Is there no defines for these?
It is, but if you look at cover we did that here so that we can get
these merged and not worry about dependency. The defines are in clock
tree. After next cycle these will be replaced with defines.
--
~Vinod
On 20-08-19, 14:27, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:11PM +0530, Vinod Koul wrote:
> > PMIC pm8150b is a slave pmic and this adds base DTS file for pm8150b
> > with pon, adc, and gpio nodes
>
> All of your other commit messages refers to it as power-on
> instead of pon, be consistent.
I missed this one, will updated :)
--
~Vinod
On 20-08-19, 14:27, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:10PM +0530, Vinod Koul wrote:
> > Add base DTS file for pm8150 along with GPIOs, power-on, rtc and vadc
> > nodes
> >
> > Signed-off-by: Vinod Koul <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/pm8150.dtsi | 95 ++++++++++++++++++++++++++++
> > 1 file changed, 95 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> > new file mode 100644
> > index 000000000000..4a678be46d37
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> > +// Copyright (c) 2019, Linaro Limited
> > +
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/spmi/spmi.h>
> > +#include <dt-bindings/iio/qcom,spmi-vadc.h>
> > +
> > +&spmi_bus {
> > + pm8150_0: pmic@0 {
> > + compatible = "qcom,pm8150", "qcom,spmi-pmic";
> > + reg = <0x0 SPMI_USID>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + pon: power-on@800 {
> > + compatible = "qcom,pm8916-pon";
> > + reg = <0x0800>;
> > + pwrkey {
> > + compatible = "qcom,pm8941-pwrkey";
> > + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
>
> Here you use 0 for 3rd cell
>
> > + debounce = <15625>;
> > + bias-pull-up;
> > + linux,code = <KEY_POWER>;
> > +
> > + status = "disabled";
> > + };
> > + };
> > +
> > + pm8150_adc: adc@3100 {
> > + compatible = "qcom,spmi-adc5";
> > + reg = <0x3100>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #io-channel-cells = <1>;
> > + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
>
> Here you use 0x0 for 3rd cell, be consistent.
Will make it either at this and other places, thanks for pointing!
--
~Vinod
On 20-08-19, 14:26, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:13PM +0530, Vinod Koul wrote:
> > This add base DTS file for sm8150-mtp and enables boot to console, adds
> > tlmm reserved range, resin node, volume down key and also includes pmic
> > file.
> >
> > Signed-off-by: Vinod Koul <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/Makefile | 1 +
> > arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 48 +++++++++++++++++++++++++
> > 2 files changed, 49 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> >
> > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> > index 0a7e5dfce6f7..1964dacaf19b 100644
> > --- a/arch/arm64/boot/dts/qcom/Makefile
> > +++ b/arch/arm64/boot/dts/qcom/Makefile
> > @@ -12,5 +12,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> > +dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> > new file mode 100644
> > index 000000000000..80b15f4f07c8
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
> > @@ -0,0 +1,48 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> > +// Copyright (c) 2019, Linaro Limited
> > +
> > +/dts-v1/;
> > +
> > +#include "sm8150.dtsi"
> > +#include "pm8150.dtsi"
> > +#include "pm8150b.dtsi"
> > +#include "pm8150l.dtsi"
> > +
> > +/ {
> > + model = "Qualcomm Technologies, Inc. SM8150 MTP";
> > + compatible = "qcom,sm8150-mtp";
> > +
> > + aliases {
> > + serial0 = &uart2;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +};
> > +
> > +&qupv3_id_1 {
> > + status = "okay";
> > +};
> > +
> > +&pon {
> > + pwrkey {
> > + status = "okay";
> > + };
> > +
> > + resin {
> > + compatible = "qcom,pm8941-resin";
> > + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
> > + debounce = <15625>;
> > + bias-pull-up;
> > + linux,code = <KEY_VOLUMEDOWN>;
> > + };
> > +};
>
> Missing a newline here.
Yup will updated
--
~Vinod
On 20-08-19, 14:26, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:14PM +0530, Vinod Koul wrote:
> > Add the regulators found in the mtp platform. This platform consists of
> > pmic PM8150, PM8150L and PM8009.
>
> Is there a reason not to squash this this patch 5/8 ?
I typically like big chunks to split logically so that is the reason why
I still kept this off from base dts one
--
~Vinod
On 20-08-19, 14:28, Niklas Cassel wrote:
> On Tue, Aug 20, 2019 at 12:12:08PM +0530, Vinod Koul wrote:
> > This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
> > the MTP for SM8150.
> >
> > Changes in v2:
> > - Squash patches
> > - Fix comments given by Stephen namely, lowercase for hext numbers,
> > making rpmhcc have xo_board as parent, rename pon controller to
> > power-on controller, make pmic nodes as disabled etc.
> > - removed the dependency on clk defines and use raw numbers
> >
> > Vinod Koul (8):
> > arm64: dts: qcom: sm8150: add base dts file
> > arm64: dts: qcom: pm8150: Add Base DTS file
> > arm64: dts: qcom: pm8150b: Add Base DTS file
> > arm64: dts: qcom: pm8150l: Add Base DTS file
> > arm64: dts: qcom: sm8150-mtp: add base dts file
>
> Use consistent naming.
Will do :)
Thanks for the review Niklas
--
~Vinod
On Tue, Aug 20, 2019 at 12:14 PM Vinod Koul <[email protected]> wrote:
>
> This add base DTS file with cpu, psci, firmware, clock, tlmm and
> spmi nodes which enables boot to console
>
> Signed-off-by: Vinod Koul <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++++++++++++++++++++++++++
> 1 file changed, 305 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> new file mode 100644
> index 000000000000..d9dc95f851b7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: BSD-3-Clause
This is fine.
> +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> +// Copyright (c) 2019, Linaro Limited
These two lines should be in /* */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <38400000>;
> + clock-output-names = "xo_board";
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + clock-output-names = "sleep_clk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> +
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo485";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> + };
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-sm8150", "qcom,scm";
> + #reset-cells = <1>;
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + soc: soc@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sm8150";
> + reg = <0x00100000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clock-names = "bi_tcxo",
> + "sleep_clk";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>;
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x00ac0000 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc 123>,
> + <&gcc 124>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + uart2: serial@a90000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x00a90000 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc 105>;
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3100000 {
> + compatible = "qcom,sm8150-pinctrl";
> + reg = <0x03100000 0x300000>,
> + <0x03500000 0x300000>,
> + <0x03900000 0x300000>,
> + <0x03d00000 0x300000>;
> + reg-names = "west", "east", "north", "south";
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-ranges = <&tlmm 0 0 175>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x17a00000 0x10000>, /* GICD */
> + <0x17a60000 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer@17c20000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x17c20000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@17c21000{
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c21000 0x1000>,
> + <0x17c22000 0x1000>;
> + };
> +
> + frame@17c23000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c23000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c25000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c25000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c27000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c26000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c29000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c29000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2b000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17c2d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x17c2d000 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0x0c440000 0x0001100>,
> + <0x0c600000 0x2000000>,
> + <0x0e600000 0x0100000>,
> + <0x0e700000 0x00a0000>,
> + <0x0c40a000 0x0026000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + cell-index = <0>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
Any particular reason why these are defined in this order - 1, 2, 3, 0?
> + };
> +};
> --
> 2.20.1
>
On 20-08-19, 19:03, Amit Kucheria wrote:
> On Tue, Aug 20, 2019 at 12:14 PM Vinod Koul <[email protected]> wrote:
> >
> > This add base DTS file with cpu, psci, firmware, clock, tlmm and
> > spmi nodes which enables boot to console
> >
> > Signed-off-by: Vinod Koul <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++++++++++++++++++++++++++
> > 1 file changed, 305 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > new file mode 100644
> > index 000000000000..d9dc95f851b7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
>
> This is fine.
>
> > +// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
> > +// Copyright (c) 2019, Linaro Limited
>
> These two lines should be in /* */
Yeah I made it same as previous, lets do right style.
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
>
> Any particular reason why these are defined in this order - 1, 2, 3, 0?
Copied from downstream :)
--
~Vinod