The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management. It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.
Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <[email protected]>
---
arch/riscv/mm/Makefile | 1 -
drivers/edac/Kconfig | 2 +-
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/sifive/Kconfig | 10 ++++++++++
drivers/soc/sifive/Makefile | 4 ++++
.../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0
7 files changed, 17 insertions(+), 2 deletions(-)
create mode 100644 drivers/soc/sifive/Kconfig
create mode 100644 drivers/soc/sifive/Makefile
rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%)
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 74055e1d6f21..d2101d0741d4 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -11,6 +11,5 @@ obj-y += extable.o
obj-y += ioremap.o
obj-y += cacheflush.o
obj-y += context.o
-obj-y += sifive_l2_cache.o
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 200c04ce5b0e..9241b3e7a050 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
config EDAC_SIFIVE
bool "Sifive platform EDAC driver"
- depends on EDAC=y && RISCV
+ depends on EDAC=y && SIFIVE_L2
help
Support for error detection and correction on the SiFive SoCs.
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 833e04a7835c..1778f8c62861 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig"
source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig"
+source "drivers/soc/sifive/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 2ec355003524..8b49d782a1ab 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -20,6 +20,7 @@ obj-y += qcom/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
+obj-$(CONFIG_SOC_SIFIVE) += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
new file mode 100644
index 000000000000..9ffb2e8a48cd
--- /dev/null
+++ b/drivers/soc/sifive/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+
+if SOC_SIFIVE
+
+config SIFIVE_L2
+ tristate "Sifive L2 Cache controller"
+ help
+ Support for the L2 cache controller on SiFive platforms.
+
+endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
new file mode 100644
index 000000000000..9b4a85558347
--- /dev/null
+++ b/drivers/soc/sifive/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
+
diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
similarity index 100%
rename from arch/riscv/mm/sifive_l2_cache.c
rename to drivers/soc/sifive/sifive_l2_cache.c
--
2.20.1
On Sun, Aug 18, 2019 at 2:01 PM Christoph Hellwig <[email protected]> wrote:
>
> The sifive_l2_cache.c is in no way related to RISC-V architecture
> memory management. It is a little stub driver working around the fact
> that the EDAC maintainers prefer their drivers to be structured in a
> certain way that doesn't fit the SiFive SOCs.
>
> Move the file to drivers/soc and add a Kconfig option for it, as well
> as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
>
> Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> Signed-off-by: Christoph Hellwig <[email protected]>
> ---
> arch/riscv/mm/Makefile | 1 -
> drivers/edac/Kconfig | 2 +-
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/sifive/Kconfig | 10 ++++++++++
> drivers/soc/sifive/Makefile | 4 ++++
> .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0
> 7 files changed, 17 insertions(+), 2 deletions(-)
> create mode 100644 drivers/soc/sifive/Kconfig
> create mode 100644 drivers/soc/sifive/Makefile
> rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%)
>
> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> index 74055e1d6f21..d2101d0741d4 100644
> --- a/arch/riscv/mm/Makefile
> +++ b/arch/riscv/mm/Makefile
> @@ -11,6 +11,5 @@ obj-y += extable.o
> obj-y += ioremap.o
> obj-y += cacheflush.o
> obj-y += context.o
> -obj-y += sifive_l2_cache.o
>
> obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 200c04ce5b0e..9241b3e7a050 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
>
> config EDAC_SIFIVE
> bool "Sifive platform EDAC driver"
> - depends on EDAC=y && RISCV
> + depends on EDAC=y && SIFIVE_L2
> help
> Support for error detection and correction on the SiFive SoCs.
>
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index 833e04a7835c..1778f8c62861 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig"
> source "drivers/soc/renesas/Kconfig"
> source "drivers/soc/rockchip/Kconfig"
> source "drivers/soc/samsung/Kconfig"
> +source "drivers/soc/sifive/Kconfig"
> source "drivers/soc/sunxi/Kconfig"
> source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 2ec355003524..8b49d782a1ab 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -20,6 +20,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> +obj-$(CONFIG_SOC_SIFIVE) += sifive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> new file mode 100644
> index 000000000000..9ffb2e8a48cd
> --- /dev/null
> +++ b/drivers/soc/sifive/Kconfig
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +if SOC_SIFIVE
> +
> +config SIFIVE_L2
> + tristate "Sifive L2 Cache controller"
> + help
> + Support for the L2 cache controller on SiFive platforms.
> +
> +endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> new file mode 100644
> index 000000000000..9b4a85558347
> --- /dev/null
> +++ b/drivers/soc/sifive/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> +
> diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> similarity index 100%
> rename from arch/riscv/mm/sifive_l2_cache.c
> rename to drivers/soc/sifive/sifive_l2_cache.c
> --
> 2.20.1
>
LGTM.
Reviewed-by: Anup Patel <[email protected]>
Regards,
Anup
On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> The sifive_l2_cache.c is in no way related to RISC-V architecture
> memory management. It is a little stub driver working around the fact
> that the EDAC maintainers prefer their drivers to be structured in a
> certain way
That changed recently so I guess we can do the per-IP block driver after
all, if people would still prefer it.
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > memory management. It is a little stub driver working around the fact
> > that the EDAC maintainers prefer their drivers to be structured in a
> > certain way
>
> That changed recently so I guess we can do the per-IP block driver after
> all, if people would still prefer it.
That would seem like the best idea. But I don't really know this code
well enough myself, and I really need to get this code out of the
forced on RISC-V codebase as some SOCs I'm working with simply don't
have the memory for it..
So unless someone signs up to do a per-IP block edac drivers instead
very quickly I'd still like to see something like this go into 5.4
for now.
On Mon, Aug 19, 2019 at 11:56 AM Christoph Hellwig <[email protected]> wrote:
>
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management. It is a little stub driver working around the fact
> > > that the EDAC maintainers prefer their drivers to be structured in a
> > > certain way
> >
> > That changed recently so I guess we can do the per-IP block driver after
> > all, if people would still prefer it.
>
> That would seem like the best idea. But I don't really know this code
> well enough myself, and I really need to get this code out of the
> forced on RISC-V codebase as some SOCs I'm working with simply don't
> have the memory for it..
>
> So unless someone signs up to do a per-IP block edac drivers instead
> very quickly I'd still like to see something like this go into 5.4
> for now.
As of now, we can pull this patch into 5.4. Later, I will review if
per-IP block edac driver is needed and if so, will take care of
implementing it.
- Yash
Em Mon, 19 Aug 2019 08:26:19 +0200
Christoph Hellwig <[email protected]> escreveu:
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management. It is a little stub driver working around the fact
> > > that the EDAC maintainers prefer their drivers to be structured in a
> > > certain way
> >
> > That changed recently so I guess we can do the per-IP block driver after
> > all, if people would still prefer it.
>
> That would seem like the best idea. But I don't really know this code
> well enough myself, and I really need to get this code out of the
> forced on RISC-V codebase as some SOCs I'm working with simply don't
> have the memory for it..
>
> So unless someone signs up to do a per-IP block edac drivers instead
> very quickly I'd still like to see something like this go into 5.4
> for now.
I'm wandering if we should at least add an entry for this one at
MAINTAINERS, pointing it to the EDAC mailing list. Something like:
diff --git a/MAINTAINERS b/MAINTAINERS
index 7dfe381c8b43..1c3bc5aa3af0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5906,6 +5906,7 @@ M: Yash Shah <[email protected]>
L: [email protected]
S: Supported
F: drivers/edac/sifive_edac.c
+F: drivers/soc/sifive/
EDAC-SKYLAKE
M: Tony Luck <[email protected]>
Thanks,
Mauro
Hi Mauro,
On Thu, 22 Aug 2019, Mauro Carvalho Chehab wrote:
> I'm wandering if we should at least add an entry for this one at
> MAINTAINERS, pointing it to the EDAC mailing list. Something like:
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7dfe381c8b43..1c3bc5aa3af0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5906,6 +5906,7 @@ M: Yash Shah <[email protected]>
> L: [email protected]
> S: Supported
> F: drivers/edac/sifive_edac.c
> +F: drivers/soc/sifive/
>
> EDAC-SKYLAKE
> M: Tony Luck <[email protected]>
There's already a MAINTAINERS entry that should cover drivers/soc/sifive.
Probably it's not needed to add another one here.
- Paul
On Fri, Aug 30, 2019 at 07:53:17PM -0700, Paul Walmsley wrote:
> There's already a MAINTAINERS entry that should cover drivers/soc/sifive.
> Probably it's not needed to add another one here.
So are you going to apply the original patch to the riscv tree?
I dont want to keep this file lingering around as a force built part
of the riscv build for another merge window.
On Sun, 18 Aug 2019, Christoph Hellwig wrote:
> The sifive_l2_cache.c is in no way related to RISC-V architecture
> memory management. It is a little stub driver working around the fact
> that the EDAC maintainers prefer their drivers to be structured in a
> certain way that doesn't fit the SiFive SOCs.
>
> Move the file to drivers/soc and add a Kconfig option for it, as well
> as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
The code in the patch looks OK to me. However, two topics that need
action:
- Since the patch doesn't fix any bugs, there shouldn't be a Fixes: line.
Please let me know whether I can drop the line locally before I apply the
patch, or whether you'd like to resend it.
- Since the patch touches drivers/edac/Kconfig, it needs to be acked by
the EDAC maintainers. I've added them to this message, but I need you to
do the work of chasing down the ack, as is standard Linux practice.
If we can get those within the next few days, I'll add it to the queue for
v5.4-rc1.
thanks -
- Paul
>
> Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> Signed-off-by: Christoph Hellwig <[email protected]>
> ---
> arch/riscv/mm/Makefile | 1 -
> drivers/edac/Kconfig | 2 +-
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/sifive/Kconfig | 10 ++++++++++
> drivers/soc/sifive/Makefile | 4 ++++
> .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0
> 7 files changed, 17 insertions(+), 2 deletions(-)
> create mode 100644 drivers/soc/sifive/Kconfig
> create mode 100644 drivers/soc/sifive/Makefile
> rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%)
>
> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> index 74055e1d6f21..d2101d0741d4 100644
> --- a/arch/riscv/mm/Makefile
> +++ b/arch/riscv/mm/Makefile
> @@ -11,6 +11,5 @@ obj-y += extable.o
> obj-y += ioremap.o
> obj-y += cacheflush.o
> obj-y += context.o
> -obj-y += sifive_l2_cache.o
>
> obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 200c04ce5b0e..9241b3e7a050 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
>
> config EDAC_SIFIVE
> bool "Sifive platform EDAC driver"
> - depends on EDAC=y && RISCV
> + depends on EDAC=y && SIFIVE_L2
> help
> Support for error detection and correction on the SiFive SoCs.
>
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index 833e04a7835c..1778f8c62861 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig"
> source "drivers/soc/renesas/Kconfig"
> source "drivers/soc/rockchip/Kconfig"
> source "drivers/soc/samsung/Kconfig"
> +source "drivers/soc/sifive/Kconfig"
> source "drivers/soc/sunxi/Kconfig"
> source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 2ec355003524..8b49d782a1ab 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -20,6 +20,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> +obj-$(CONFIG_SOC_SIFIVE) += sifive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> new file mode 100644
> index 000000000000..9ffb2e8a48cd
> --- /dev/null
> +++ b/drivers/soc/sifive/Kconfig
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +if SOC_SIFIVE
> +
> +config SIFIVE_L2
> + tristate "Sifive L2 Cache controller"
> + help
> + Support for the L2 cache controller on SiFive platforms.
> +
> +endif
> diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
> new file mode 100644
> index 000000000000..9b4a85558347
> --- /dev/null
> +++ b/drivers/soc/sifive/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o
> +
> diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> similarity index 100%
> rename from arch/riscv/mm/sifive_l2_cache.c
> rename to drivers/soc/sifive/sifive_l2_cache.c
> --
> 2.20.1
>
>
One other comment on this patch:
On Fri, 6 Sep 2019, Paul Walmsley wrote:
> On Sun, 18 Aug 2019, Christoph Hellwig wrote:
>
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> > index 200c04ce5b0e..9241b3e7a050 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
> >
> > config EDAC_SIFIVE
> > bool "Sifive platform EDAC driver"
> > - depends on EDAC=y && RISCV
> > + depends on EDAC=y && SIFIVE_L2
Since the guidance from the EDAC maintainers is that this driver is to be
a platform driver -- which would, for example, also include EDAC support for
other IP blocks (e.g., DRAM controllers) on SiFive SoCs -- this should
depend on SOC_SIFIVE, not SIFIVE_L2.
- Paul
On Mon, 19 Aug 2019, Christoph Hellwig wrote:
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management. It is a little stub driver working around the fact
> > > that the EDAC maintainers prefer their drivers to be structured in a
> > > certain way
> >
> > That changed recently so I guess we can do the per-IP block driver after
> > all, if people would still prefer it.
>
> That would seem like the best idea. But I don't really know this code
> well enough myself, and I really need to get this code out of the
> forced on RISC-V codebase as some SOCs I'm working with simply don't
> have the memory for it..
If that's your primary concern, then in the short term, how about just
sending a single-line patch to the arch/riscv/mm Makefile to skip building
it if !CONFIG_SOC_SIFIVE? Assuming, that is, you won't be enabling EDAC
support for those low-end SoCs. Then you won't need to get the ack
from the EDAC folks in the short term.
Then a patch to make the SiFive platform EDAC driver build contingent on
CONFIG_SOC_SIFIVE could be sent separately.
- Paul
On Fri, Sep 06, 2019 at 03:33:02PM -0700, Paul Walmsley wrote:
> If that's your primary concern, then in the short term, how about just
> sending a single-line patch to the arch/riscv/mm Makefile to skip building
> it if !CONFIG_SOC_SIFIVE? Assuming, that is, you won't be enabling EDAC
> support for those low-end SoCs. Then you won't need to get the ack
> from the EDAC folks in the short term.
Paul, stop it. The patch that meged this was complete crap and fucked up.
And instead of just fixing up this mess ASAP you just keep arguing even
when I finally get hold of a RISC-V maintainer after weeks of waiting.
If this isn't going to get any better I'm just going to bypass you for
RISC-V patches and will send patches straight to Linus.
On Fri, Sep 06, 2019 at 03:27:44PM -0700, Paul Walmsley wrote:
> - Since the patch doesn't fix any bugs, there shouldn't be a Fixes: line.
> Please let me know whether I can drop the line locally before I apply the
> patch, or whether you'd like to resend it.
It fixes the bug that we build code into a default RISC-V image that
we absolutely should not. And it fixes the bug that the patch placed
code in absolutely the wrong place.
On Fri, Sep 06, 2019 at 03:36:09PM -0700, Paul Walmsley wrote:
> One other comment on this patch:
>
> On Fri, 6 Sep 2019, Paul Walmsley wrote:
>
> > On Sun, 18 Aug 2019, Christoph Hellwig wrote:
> >
> > > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> > > index 200c04ce5b0e..9241b3e7a050 100644
> > > --- a/drivers/edac/Kconfig
> > > +++ b/drivers/edac/Kconfig
> > > @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
> > >
> > > config EDAC_SIFIVE
> > > bool "Sifive platform EDAC driver"
> > > - depends on EDAC=y && RISCV
> > > + depends on EDAC=y && SIFIVE_L2
>
> Since the guidance from the EDAC maintainers is that this driver is to be
> a platform driver -- which would, for example, also include EDAC support for
> other IP blocks (e.g., DRAM controllers) on SiFive SoCs -- this should
> depend on SOC_SIFIVE, not SIFIVE_L2.
But as-is without major changes it depends on SIFIVE_L2. And given that
it supports nothing else as-is there is no point in making the code
conditional either.
On Thu, Aug 22, 2019 at 06:26:35AM -0300, Mauro Carvalho Chehab wrote:
> Em Mon, 19 Aug 2019 08:26:19 +0200
> Christoph Hellwig <[email protected]> escreveu:
>
> > On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > > memory management. It is a little stub driver working around the fact
> > > > that the EDAC maintainers prefer their drivers to be structured in a
> > > > certain way
> > >
> > > That changed recently so I guess we can do the per-IP block driver after
> > > all, if people would still prefer it.
> >
> > That would seem like the best idea. But I don't really know this code
> > well enough myself, and I really need to get this code out of the
> > forced on RISC-V codebase as some SOCs I'm working with simply don't
> > have the memory for it..
> >
> > So unless someone signs up to do a per-IP block edac drivers instead
> > very quickly I'd still like to see something like this go into 5.4
> > for now.
>
> I'm wandering if we should at least add an entry for this one at
> MAINTAINERS, pointing it to the EDAC mailing list. Something like:
Sounds fine. Can you also ACK the patch with that, as Paul mention
in another thread he wants an EDAC ACK for it.
Mauro, can you Ack this patch?
On Sat, Sep 28, 2019 at 12:53:04AM +0200, Christoph Hellwig wrote:
> > > well enough myself, and I really need to get this code out of the
> > > forced on RISC-V codebase as some SOCs I'm working with simply don't
> > > have the memory for it..
> > >
> > > So unless someone signs up to do a per-IP block edac drivers instead
> > > very quickly I'd still like to see something like this go into 5.4
> > > for now.
> >
> > I'm wandering if we should at least add an entry for this one at
> > MAINTAINERS, pointing it to the EDAC mailing list. Something like:
>
> Sounds fine. Can you also ACK the patch with that, as Paul mention
> in another thread he wants an EDAC ACK for it.
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