Thank you Vignesh for the valuable review comments.
changes from v2:
The following review comments are addressed.
1. implemented quirks for intel lgm soc.
2. removed the DT entry based checks.
3. removed the trigger_address in unneccessary places.
4. qspi string removed instead add NULL(originally)
5. removed CQSPI_REG_CONFIG_DMA_MASK
6. changed the commit message.
Ramuthevar Vadivel Murugan (3):
dt-bindings: mtd: cadence-qspi:add support for Intel lgm-qspi
mtd: spi-nor: cadence-quadspi: Disable the DAC for Intel LGM SoC
mtd: spi-nor: cadence-quadspi: disable the auto-poll for Intel LGM
.../devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
drivers/mtd/spi-nor/Kconfig | 2 +-
drivers/mtd/spi-nor/cadence-quadspi.c | 45 ++++++++++++++++++++++
3 files changed, 47 insertions(+), 1 deletion(-)
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
on Intel's Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch introduces to properly disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
drivers/mtd/spi-nor/Kconfig | 2 +-
drivers/mtd/spi-nor/cadence-quadspi.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 6de83277ce8b..ba2e372ae514 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -34,7 +34,7 @@ config SPI_ASPEED_SMC
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || COMPILE_TEST)
+ depends on OF && (ARM || ARM64 || COMPILE_TEST || X86)
help
Enable support for the Cadence Quad SPI Flash controller.
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 67f15a1f16fd..73b9fbd1508a 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -33,6 +33,7 @@
/* Quirks */
#define CQSPI_NEEDS_WR_DELAY BIT(0)
+#define CQSPI_DISABLE_DAC_MODE BIT(1)
/* Capabilities mask */
#define CQSPI_BASE_HWCAPS_MASK \
@@ -609,6 +610,13 @@ static int cqspi_write_setup(struct spi_nor *nor)
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
+ /* Disable direct access controller */
+ if (!f_pdata->use_direct_mode) {
+ reg = readl(reg_base + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, reg_base + CQSPI_REG_CONFIG);
+ }
+
/* Set opcode. */
reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, reg_base + CQSPI_REG_WR_INSTR);
@@ -1328,6 +1336,7 @@ static int cqspi_probe(struct platform_device *pdev)
struct resource *res_ahb;
struct reset_control *rstc, *rstc_ocp;
const struct cqspi_driver_platdata *ddata;
+ struct cqspi_flash_pdata *f_pdata;
int ret;
int irq;
@@ -1436,6 +1445,9 @@ static int cqspi_probe(struct platform_device *pdev)
goto probe_setup_failed;
}
+ if (ddata && (ddata->quirks & CQSPI_DISABLE_DAC_MODE))
+ f_pdata->use_direct_mode = false;
+
return ret;
probe_setup_failed:
cqspi_controller_enable(cqspi, 0);
@@ -1510,6 +1522,11 @@ static const struct cqspi_driver_platdata am654_ospi = {
.quirks = CQSPI_NEEDS_WR_DELAY,
};
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
+ .quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1523,6 +1540,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "ti,am654-ospi",
.data = &am654_ospi,
},
+ {
+ .compatible = "intel,lgm-qspi",
+ .data = &intel_lgm_qspi,
+ },
{ /* end of table */ }
};
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
Add new vendor specific compatible string to check Intel's Lightning
Mountain(LGM) QSPI features enablement in cadence-quadspi driver.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index 945be7d5b236..8ace832a2d80 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -5,6 +5,7 @@ Required properties:
Generic default - "cdns,qspi-nor".
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
+ For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
On Intel's Lightning Mountain(LGM) SoC QSPI controller do not auto-poll.
This patch introduces to properly disable the auto-polling feature to
improve the performance of cadence-quadspi.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 73b9fbd1508a..60998eaad1cc 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -135,6 +135,8 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
+#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
+#define CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL BIT(14)
#define CQSPI_REG_WR_INSTR 0x08
#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
@@ -471,6 +473,18 @@ static int cqspi_command_write_addr(struct spi_nor *nor,
return cqspi_exec_flash_cmd(cqspi, reg);
}
+static int cqspi_disable_auto_poll(struct cqspi_st *cqspi)
+{
+ void __iomem *reg_base = cqspi->iobase;
+ unsigned int reg;
+
+ reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
+ reg |= CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL;
+ writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
+
+ return 0;
+}
+
static int cqspi_read_setup(struct spi_nor *nor)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
@@ -508,6 +522,11 @@ static int cqspi_read_setup(struct spi_nor *nor)
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (nor->addr_width - 1);
writel(reg, reg_base + CQSPI_REG_SIZE);
+
+ /* Disable auto-polling */
+ if (!f_pdata->use_direct_mode)
+ cqspi_disable_auto_poll(cqspi);
+
return 0;
}
@@ -627,6 +646,11 @@ static int cqspi_write_setup(struct spi_nor *nor)
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (nor->addr_width - 1);
writel(reg, reg_base + CQSPI_REG_SIZE);
+
+ /* Disable auto-polling */
+ if (!f_pdata->use_direct_mode)
+ cqspi_disable_auto_poll(cqspi);
+
return 0;
}
--
2.11.0
On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <[email protected]>
>
> on Intel's Lightning Mountain(LGM) SoCs QSPI controller do not use
s/on/On
> Direct Access Controller(DAC).
>
> This patch introduces to properly disable the Direct Access Controller
"This patch adds a quirk to disable..." or something something similar
> for data transfer instead it uses indirect data transfer.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
> ---
> drivers/mtd/spi-nor/Kconfig | 2 +-
> drivers/mtd/spi-nor/cadence-quadspi.c | 21 +++++++++++++++++++++
> 2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 6de83277ce8b..ba2e372ae514 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -34,7 +34,7 @@ config SPI_ASPEED_SMC
>
> config SPI_CADENCE_QUADSPI
> tristate "Cadence Quad SPI controller"
> - depends on OF && (ARM || ARM64 || COMPILE_TEST)
> + depends on OF && (ARM || ARM64 || COMPILE_TEST || X86)
> help
> Enable support for the Cadence Quad SPI Flash controller.
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 67f15a1f16fd..73b9fbd1508a 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -33,6 +33,7 @@
>
> /* Quirks */
> #define CQSPI_NEEDS_WR_DELAY BIT(0)
> +#define CQSPI_DISABLE_DAC_MODE BIT(1)
>
> /* Capabilities mask */
> #define CQSPI_BASE_HWCAPS_MASK \
> @@ -609,6 +610,13 @@ static int cqspi_write_setup(struct spi_nor *nor)
> struct cqspi_st *cqspi = f_pdata->cqspi;
> void __iomem *reg_base = cqspi->iobase;
>
> + /* Disable direct access controller */
> + if (!f_pdata->use_direct_mode) {
> + reg = readl(reg_base + CQSPI_REG_CONFIG);
> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, reg_base + CQSPI_REG_CONFIG);
> + }
> +
> /* Set opcode. */
> reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
> writel(reg, reg_base + CQSPI_REG_WR_INSTR);
> @@ -1328,6 +1336,7 @@ static int cqspi_probe(struct platform_device *pdev)
> struct resource *res_ahb;
> struct reset_control *rstc, *rstc_ocp;
> const struct cqspi_driver_platdata *ddata;
> + struct cqspi_flash_pdata *f_pdata;
> int ret;
> int irq;
>
> @@ -1436,6 +1445,9 @@ static int cqspi_probe(struct platform_device *pdev)
> goto probe_setup_failed;
> }
>
> + if (ddata && (ddata->quirks & CQSPI_DISABLE_DAC_MODE))
> + f_pdata->use_direct_mode = false;
> +
If you do this here, you will still end up acquiring a DMA channel in
cqspi_request_mmap_dma() (called from cqspi_setup_flash()). So, please
move the check to cqspi_setup_flash().
> return ret;
> probe_setup_failed:
> cqspi_controller_enable(cqspi, 0);
> @@ -1510,6 +1522,11 @@ static const struct cqspi_driver_platdata am654_ospi = {
> .quirks = CQSPI_NEEDS_WR_DELAY,
> };
>
> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
> + .quirks = CQSPI_DISABLE_DAC_MODE,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> @@ -1523,6 +1540,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
> .compatible = "ti,am654-ospi",
> .data = &am654_ospi,
> },
> + {
> + .compatible = "intel,lgm-qspi",
> + .data = &intel_lgm_qspi,
> + },
> { /* end of table */ }
> };
>
>
--
Regards
Vignesh
On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <[email protected]>
>
> On Intel's Lightning Mountain(LGM) SoC QSPI controller do not auto-poll.
> This patch introduces to properly disable the auto-polling feature to
This patch disables auto polling when direct access mode is disabled
which should be noted in the commit message.
> improve the performance of cadence-quadspi.
How does this improve performance of cadence-quadspi? I would expect HW
auto-polling to be faster than SW polling.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 73b9fbd1508a..60998eaad1cc 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -135,6 +135,8 @@ struct cqspi_driver_platdata {
> #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
> #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
>
> +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
> +#define CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL BIT(14)
> #define CQSPI_REG_WR_INSTR 0x08
> #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
> #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
> @@ -471,6 +473,18 @@ static int cqspi_command_write_addr(struct spi_nor *nor,
> return cqspi_exec_flash_cmd(cqspi, reg);
> }
>
> +static int cqspi_disable_auto_poll(struct cqspi_st *cqspi)
> +{
> + void __iomem *reg_base = cqspi->iobase;
> + unsigned int reg;
> +
> + reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> + reg |= CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL;
> + writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
> +
> + return 0;
> +}
> +
> static int cqspi_read_setup(struct spi_nor *nor)
> {
> struct cqspi_flash_pdata *f_pdata = nor->priv;
> @@ -508,6 +522,11 @@ static int cqspi_read_setup(struct spi_nor *nor)
> reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
> reg |= (nor->addr_width - 1);
> writel(reg, reg_base + CQSPI_REG_SIZE);
> +
> + /* Disable auto-polling */
> + if (!f_pdata->use_direct_mode)
> + cqspi_disable_auto_poll(cqspi);
> +
> return 0;
> }
>
Hmmm.. There is no need to disable polling for every read/write
operation. It should be enough to do it once in cqspi_controller_init()
> @@ -627,6 +646,11 @@ static int cqspi_write_setup(struct spi_nor *nor)
> reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
> reg |= (nor->addr_width - 1);
> writel(reg, reg_base + CQSPI_REG_SIZE);
> +
> + /* Disable auto-polling */
> + if (!f_pdata->use_direct_mode)
> + cqspi_disable_auto_poll(cqspi);
> +
> return 0;
> }
>
>
--
Regards
Vignesh
Hi Vignesh,
Thank you for the review comments.
On 16/10/2019 4:32 PM, Vignesh Raghavendra wrote:
>
> On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <[email protected]>
>>
>> on Intel's Lightning Mountain(LGM) SoCs QSPI controller do not use
> s/on/On
Agreed, will update.
>> Direct Access Controller(DAC).
>>
>> This patch introduces to properly disable the Direct Access Controller
> "This patch adds a quirk to disable..." or something something similar
okay, will update.
>> for data transfer instead it uses indirect data transfer.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
>> ---
>> drivers/mtd/spi-nor/Kconfig | 2 +-
>> drivers/mtd/spi-nor/cadence-quadspi.c | 21 +++++++++++++++++++++
>> 2 files changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
>> index 6de83277ce8b..ba2e372ae514 100644
>> --- a/drivers/mtd/spi-nor/Kconfig
>> +++ b/drivers/mtd/spi-nor/Kconfig
>> @@ -34,7 +34,7 @@ config SPI_ASPEED_SMC
>>
>> config SPI_CADENCE_QUADSPI
>> tristate "Cadence Quad SPI controller"
>> - depends on OF && (ARM || ARM64 || COMPILE_TEST)
>> + depends on OF && (ARM || ARM64 || COMPILE_TEST || X86)
>> help
>> Enable support for the Cadence Quad SPI Flash controller.
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 67f15a1f16fd..73b9fbd1508a 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -33,6 +33,7 @@
>>
>> /* Quirks */
>> #define CQSPI_NEEDS_WR_DELAY BIT(0)
>> +#define CQSPI_DISABLE_DAC_MODE BIT(1)
>>
>> /* Capabilities mask */
>> #define CQSPI_BASE_HWCAPS_MASK \
>> @@ -609,6 +610,13 @@ static int cqspi_write_setup(struct spi_nor *nor)
>> struct cqspi_st *cqspi = f_pdata->cqspi;
>> void __iomem *reg_base = cqspi->iobase;
>>
>> + /* Disable direct access controller */
>> + if (!f_pdata->use_direct_mode) {
>> + reg = readl(reg_base + CQSPI_REG_CONFIG);
>> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
>> + writel(reg, reg_base + CQSPI_REG_CONFIG);
>> + }
>> +
>> /* Set opcode. */
>> reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
>> writel(reg, reg_base + CQSPI_REG_WR_INSTR);
>> @@ -1328,6 +1336,7 @@ static int cqspi_probe(struct platform_device *pdev)
>> struct resource *res_ahb;
>> struct reset_control *rstc, *rstc_ocp;
>> const struct cqspi_driver_platdata *ddata;
>> + struct cqspi_flash_pdata *f_pdata;
>> int ret;
>> int irq;
>>
>> @@ -1436,6 +1445,9 @@ static int cqspi_probe(struct platform_device *pdev)
>> goto probe_setup_failed;
>> }
>>
>> + if (ddata && (ddata->quirks & CQSPI_DISABLE_DAC_MODE))
>> + f_pdata->use_direct_mode = false;
>> +
> If you do this here, you will still end up acquiring a DMA channel in
> cqspi_request_mmap_dma() (called from cqspi_setup_flash()). So, please
> move the check to cqspi_setup_flash().
will fix it.
---
Regards
Vadivel
>> return ret;
>> probe_setup_failed:
>> cqspi_controller_enable(cqspi, 0);
>> @@ -1510,6 +1522,11 @@ static const struct cqspi_driver_platdata am654_ospi = {
>> .quirks = CQSPI_NEEDS_WR_DELAY,
>> };
>>
>> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
>> + .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
>> + .quirks = CQSPI_DISABLE_DAC_MODE,
>> +};
>> +
>> static const struct of_device_id cqspi_dt_ids[] = {
>> {
>> .compatible = "cdns,qspi-nor",
>> @@ -1523,6 +1540,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
>> .compatible = "ti,am654-ospi",
>> .data = &am654_ospi,
>> },
>> + {
>> + .compatible = "intel,lgm-qspi",
>> + .data = &intel_lgm_qspi,
>> + },
>> { /* end of table */ }
>> };
>>
>>
Hi Vignesh,
Thank you for the review comments.
On 16/10/2019 4:40 PM, Vignesh Raghavendra wrote:
>
> On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <[email protected]>
>>
>> On Intel's Lightning Mountain(LGM) SoC QSPI controller do not auto-poll.
>> This patch introduces to properly disable the auto-polling feature to
> This patch disables auto polling when direct access mode is disabled
> which should be noted in the commit message.
will add it.
>> improve the performance of cadence-quadspi.
> How does this improve performance of cadence-quadspi? I would expect HW
> auto-polling to be faster than SW polling.
During the bring-up time observed this, once again verify it on my setup.
Agreed, you are correct HW auto-polling is faster than SW polling.
>> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
>> ---
>> drivers/mtd/spi-nor/cadence-quadspi.c | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 73b9fbd1508a..60998eaad1cc 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -135,6 +135,8 @@ struct cqspi_driver_platdata {
>> #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
>> #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
>>
>> +#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
>> +#define CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL BIT(14)
>> #define CQSPI_REG_WR_INSTR 0x08
>> #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
>> #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
>> @@ -471,6 +473,18 @@ static int cqspi_command_write_addr(struct spi_nor *nor,
>> return cqspi_exec_flash_cmd(cqspi, reg);
>> }
>>
>> +static int cqspi_disable_auto_poll(struct cqspi_st *cqspi)
>> +{
>> + void __iomem *reg_base = cqspi->iobase;
>> + unsigned int reg;
>> +
>> + reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
>> + reg |= CQSPI_REG_WR_COMPLETION_DISABLE_AUTO_POLL;
>> + writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
>> +
>> + return 0;
>> +}
>> +
>> static int cqspi_read_setup(struct spi_nor *nor)
>> {
>> struct cqspi_flash_pdata *f_pdata = nor->priv;
>> @@ -508,6 +522,11 @@ static int cqspi_read_setup(struct spi_nor *nor)
>> reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
>> reg |= (nor->addr_width - 1);
>> writel(reg, reg_base + CQSPI_REG_SIZE);
>> +
>> + /* Disable auto-polling */
>> + if (!f_pdata->use_direct_mode)
>> + cqspi_disable_auto_poll(cqspi);
>> +
>> return 0;
>> }
>>
> Hmmm.. There is no need to disable polling for every read/write
> operation. It should be enough to do it once in cqspi_controller_init()
sure, move to cqspi_controller_init() .
---
Regards
Vadivel
>
>
>> @@ -627,6 +646,11 @@ static int cqspi_write_setup(struct spi_nor *nor)
>> reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
>> reg |= (nor->addr_width - 1);
>> writel(reg, reg_base + CQSPI_REG_SIZE);
>> +
>> + /* Disable auto-polling */
>> + if (!f_pdata->use_direct_mode)
>> + cqspi_disable_auto_poll(cqspi);
>> +
>> return 0;
>> }
>>
>>