Hi all,
This is a patch set for the Exynos5 Dynamic Memory Controller
driver which could be found in Krzysztof's tree [1]. It is on top of a
merge of the two branches [1][2].
It adds interrupt mode which does not relay on devfreq polling.
Instead of checking the device state by the framework, driver uses local
performance events counters which could trigger interrupt when overflow.
Thanks to this approach the driver avoids issues present in devfreq framework,
when default polling check does not occur.
The algorithm calculates 'busy_time' and 'total_time' needed for devfreq
governors (simple_ondemand) based on requests transactions traffic.
Regards,
Lukasz Luba
[1] https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git/log/?h=for-v5.4-5.5/memory-samsung-dmc
[2] https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git/log/?h=for-v5.4-5.5/memory-samsung-dmc-dt
Lukasz Luba (3):
ARM: dts: exynos: Add interrupt to DMC controller in Exynos5422
ARM: dts: exynos: map 0x10000 SFR instead of 0x100 in DMC Exynos5422
memory: samsung: exynos5422-dmc: Add support for interrupt from
performance counters
arch/arm/boot/dts/exynos5420.dtsi | 4 +-
drivers/memory/samsung/exynos5422-dmc.c | 297 ++++++++++++++++++++++--
2 files changed, 275 insertions(+), 26 deletions(-)
--
2.17.1
Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid
XU3-family boards. It will be used instead of devfreq polling mode
governor. The interrupt is connected to performance counters private
for DMC, which might track utilisation of the memory channels.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index ac49373baae7..72738e620d11 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -240,6 +240,8 @@
dmc: memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>;
clocks = <&clock CLK_FOUT_SPLL>,
<&clock CLK_MOUT_SCLK_SPLL>,
<&clock CLK_FF_DOUT_SPLL2>,
--
2.17.1
There is a need to access registers at address offset near 0x10000.
These registers are private DMC performance counters, which might be used
as interrupt trigger when overflow. Potential usage is to skip polling
in devfreq framework and switch to interrupt managed bandwidth control.
Signed-off-by: Lukasz Luba <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 72738e620d11..b695f07f7eed 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -239,7 +239,7 @@
dmc: memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
- reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
interrupt-parent = <&combiner>;
interrupts = <16 0>;
clocks = <&clock CLK_FOUT_SPLL>,
--
2.17.1
On Wed, Sep 25, 2019 at 06:18:11PM +0200, Lukasz Luba wrote:
> Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid
> XU3-family boards. It will be used instead of devfreq polling mode
> governor. The interrupt is connected to performance counters private
> for DMC, which might track utilisation of the memory channels.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index ac49373baae7..72738e620d11 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -240,6 +240,8 @@
> dmc: memory-controller@10c20000 {
> compatible = "samsung,exynos5422-dmc";
> reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
> + interrupt-parent = <&combiner>;
> + interrupts = <16 0>;
You register DMC for DREX0 and DREX1 but take only DREX0 interrupt. Why
skipping second?
Best regards,
Krzysztof
> clocks = <&clock CLK_FOUT_SPLL>,
> <&clock CLK_MOUT_SCLK_SPLL>,
> <&clock CLK_FF_DOUT_SPLL2>,
> --
> 2.17.1
>
Hi Krzysztof,
On 9/27/19 10:53 AM, Krzysztof Kozlowski wrote:
> On Wed, Sep 25, 2019 at 06:18:11PM +0200, Lukasz Luba wrote:
>> Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid
>> XU3-family boards. It will be used instead of devfreq polling mode
>> governor. The interrupt is connected to performance counters private
>> for DMC, which might track utilisation of the memory channels.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index ac49373baae7..72738e620d11 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -240,6 +240,8 @@
>> dmc: memory-controller@10c20000 {
>> compatible = "samsung,exynos5422-dmc";
>> reg = <0x10c20000 0x100>, <0x10c30000 0x100>;
>> + interrupt-parent = <&combiner>;
>> + interrupts = <16 0>;
>
> You register DMC for DREX0 and DREX1 but take only DREX0 interrupt. Why
> skipping second?
>
Right, the second should also be there: <16 1>. The channel 1 has not
been triggered in CPU test cases but might be used by some other
NoC clients.
I will add it in the next version.
Regards,
Lukasz