Hello,
This series is similar to that for the AST2500 but I've split the patches out
as the AST2600 driver is new for 5.4 and I'm hoping we have a chance of
slipping them in. Maybe we can get both series in, but I thought decoupling
them might make it more manageable if not.
Regardless, the blurb:
This series is two small changes enable kernel support for controlling the RMII
RCLK gate on AST2600-based systems. RMII is commonly used for NCSI, which
itself is commonly used for BMC-based designs to reduce cabling requirements
for the platform. NCSI support for the AST2600 is not yet implemented in
u-boot and so unlike the AST2500 the kernel can't rely on RCLK already being
ungated.
Please review!
Andrew
Andrew Jeffery (2):
dt-bindings: clock: Add AST2600 RMII RCLK gate definitions
clk: ast2600: Add RMII RCLK gates for all four MACs
drivers/clk/clk-ast2600.c | 47 ++++++++++++++++++++++-
include/dt-bindings/clock/ast2600-clock.h | 5 +++
2 files changed, 51 insertions(+), 1 deletion(-)
--
2.20.1
The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.
Signed-off-by: Andrew Jeffery <[email protected]>
---
include/dt-bindings/clock/ast2600-clock.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 38074a5f7296..ac567fc84a87 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -84,6 +84,11 @@
#define ASPEED_CLK_MAC34 65
#define ASPEED_CLK_USBPHY_40M 66
+#define ASPEED_CLK_GATE_MAC1RCLK 67
+#define ASPEED_CLK_GATE_MAC2RCLK 68
+#define ASPEED_CLK_GATE_MAC3RCLK 69
+#define ASPEED_CLK_GATE_MAC4RCLK 70
+
/* Only list resets here that are not part of a gate */
#define ASPEED_RESET_ADC 55
#define ASPEED_RESET_JTAG_MASTER2 54
--
2.20.1
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.
Signed-off-by: Andrew Jeffery <[email protected]>
---
drivers/clk/clk-ast2600.c | 47 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 1c1bb39bb04e..3d6fc781fee0 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -15,7 +15,7 @@
#include "clk-aspeed.h"
-#define ASPEED_G6_NUM_CLKS 67
+#define ASPEED_G6_NUM_CLKS 71
#define ASPEED_G6_SILICON_REV 0x004
@@ -40,6 +40,9 @@
#define ASPEED_G6_STRAP1 0x500
+#define ASPEED_MAC12_CLK_DLY 0x340
+#define ASPEED_MAC34_CLK_DLY 0x350
+
/* Globally visible clocks */
static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
@@ -485,6 +488,11 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
+ /* MAC1/2 RMII 50MHz RCLK */
+ hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
/* MAC1/2 AHB bus clock divider */
hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
@@ -494,6 +502,27 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
+ /* RMII1 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac1rclk-gate", "mac12rclk", 0,
+ scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw;
+
+ /* RMII2 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac2rclk-gate", "mac12rclk", 0,
+ scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw;
+
+ /* MAC1/2 RMII 50MHz RCLK */
+ hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
/* MAC3/4 AHB bus clock divider */
hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
scu_g6_base + 0x310, 24, 3, 0,
@@ -503,6 +532,22 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
+ /* RMII3 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac3rclk-gate", "mac34rclk", 0,
+ scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC3RCLK] = hw;
+
+ /* RMII4 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac4rclk-gate", "mac34rclk", 0,
+ scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
+ &aspeed_g6_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC4RCLK] = hw;
+
/* LPC Host (LHCLK) clock divider */
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
--
2.20.1
On Tue, 8 Oct 2019 at 11:35, Andrew Jeffery <[email protected]> wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
We could have mac12rclk and mac34rclk described in the device tree, as
was mentioned in previous reviews of the aspeed driver, but I think we
can defer that
rework until we rework the rest of the driver. Importantly, that won't
change the MAC bindings or the code that the drivers need to use.
Reviewed-by: Joel Stanley <[email protected]>
> ---
> drivers/clk/clk-ast2600.c | 47 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 46 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
> index 1c1bb39bb04e..3d6fc781fee0 100644
> --- a/drivers/clk/clk-ast2600.c
> +++ b/drivers/clk/clk-ast2600.c
> @@ -15,7 +15,7 @@
>
> #include "clk-aspeed.h"
>
> -#define ASPEED_G6_NUM_CLKS 67
> +#define ASPEED_G6_NUM_CLKS 71
>
> #define ASPEED_G6_SILICON_REV 0x004
>
> @@ -40,6 +40,9 @@
>
> #define ASPEED_G6_STRAP1 0x500
>
> +#define ASPEED_MAC12_CLK_DLY 0x340
> +#define ASPEED_MAC34_CLK_DLY 0x350
> +
> /* Globally visible clocks */
> static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
>
> @@ -485,6 +488,11 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
> return PTR_ERR(hw);
> aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
>
> + /* MAC1/2 RMII 50MHz RCLK */
> + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> +
> /* MAC1/2 AHB bus clock divider */
> hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
> scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
> @@ -494,6 +502,27 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
> return PTR_ERR(hw);
> aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
>
> + /* RMII1 50MHz (RCLK) output enable */
> + hw = clk_hw_register_gate(dev, "mac1rclk-gate", "mac12rclk", 0,
> + scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
> + &aspeed_g6_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw;
> +
> + /* RMII2 50MHz (RCLK) output enable */
> + hw = clk_hw_register_gate(dev, "mac2rclk-gate", "mac12rclk", 0,
> + scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
> + &aspeed_g6_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw;
> +
> + /* MAC1/2 RMII 50MHz RCLK */
> + hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> +
> /* MAC3/4 AHB bus clock divider */
> hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
> scu_g6_base + 0x310, 24, 3, 0,
> @@ -503,6 +532,22 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
> return PTR_ERR(hw);
> aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
>
> + /* RMII3 50MHz (RCLK) output enable */
> + hw = clk_hw_register_gate(dev, "mac3rclk-gate", "mac34rclk", 0,
> + scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
> + &aspeed_g6_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC3RCLK] = hw;
> +
> + /* RMII4 50MHz (RCLK) output enable */
> + hw = clk_hw_register_gate(dev, "mac4rclk-gate", "mac34rclk", 0,
> + scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
> + &aspeed_g6_clk_lock);
> + if (IS_ERR(hw))
> + return PTR_ERR(hw);
> + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC4RCLK] = hw;
> +
> /* LPC Host (LHCLK) clock divider */
> hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
> scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
> --
> 2.20.1
>
On Tue, 8 Oct 2019 at 11:34, Andrew Jeffery <[email protected]> wrote:
>
> The AST2600 has an explicit gate for the RMII RCLK for each of the four
> MACs.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
> ---
> include/dt-bindings/clock/ast2600-clock.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
> index 38074a5f7296..ac567fc84a87 100644
> --- a/include/dt-bindings/clock/ast2600-clock.h
> +++ b/include/dt-bindings/clock/ast2600-clock.h
> @@ -84,6 +84,11 @@
> #define ASPEED_CLK_MAC34 65
> #define ASPEED_CLK_USBPHY_40M 66
>
> +#define ASPEED_CLK_GATE_MAC1RCLK 67
> +#define ASPEED_CLK_GATE_MAC2RCLK 68
> +#define ASPEED_CLK_GATE_MAC3RCLK 69
> +#define ASPEED_CLK_GATE_MAC4RCLK 70
My comments on the other patch about GATEs should have been on this patch.
> +
> /* Only list resets here that are not part of a gate */
> #define ASPEED_RESET_ADC 55
> #define ASPEED_RESET_JTAG_MASTER2 54
> --
> 2.20.1
>