Hello,
This series is two small changes enable kernel support for controlling the RMII
RCLK gate on AST2500-based systems. Previously the kernel has assumed u-boot
has ungated RCLK for networking to function.
RMII is commonly used for NCSI, which itself is commonly used for BMC-based
designs to reduce cabling requirements for the platform.
v2:
* Rename macros and clock names based on Joel's feedback.
v1 can be found here: https://lore.kernel.org/linux-clk/[email protected]/
Please review!
Andrew
Andrew Jeffery (2):
dt-bindings: clock: Add AST2500 RMII RCLK definitions
clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
drivers/clk/clk-aspeed.c | 27 +++++++++++++++++++++++-
include/dt-bindings/clock/aspeed-clock.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
--
2.20.1
The AST2500 has an explicit gate for the RMII RCLK for each of the two
MACs.
Signed-off-by: Andrew Jeffery <[email protected]>
---
v2: Drop "_GATE" from symbol names
include/dt-bindings/clock/aspeed-clock.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index f43738607d77..9ff4f6e4558c 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -39,6 +39,8 @@
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35
+#define ASPEED_CLK_MAC1RCLK 36
+#define ASPEED_CLK_MAC2RCLK 37
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
--
2.20.1
RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.
Signed-off-by: Andrew Jeffery <[email protected]>
---
v2: Drop "-gate" from clock names
drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index abf06fb6453e..411ff5fb2c07 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,7 @@
#include "clk-aspeed.h"
-#define ASPEED_NUM_CLKS 36
+#define ASPEED_NUM_CLKS 38
#define ASPEED_RESET2_OFFSET 32
@@ -28,6 +28,7 @@
#define AST2400_HPLL_BYPASS_EN BIT(17)
#define ASPEED_MISC_CTRL 0x2c
#define UART_DIV13_EN BIT(12)
+#define ASPEED_MAC_CLK_DLY 0x48
#define ASPEED_STRAP 0x70
#define CLKIN_25MHZ_EN BIT(23)
#define AST2400_CLK_SOURCE_SEL BIT(18)
@@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
+ if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
+ /* RMII 50MHz RCLK */
+ hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
+ 50000000);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ /* RMII1 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+ scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
+
+ /* RMII2 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+ scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
+ }
+
/* LPC Host (LHCLK) clock divider */
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
--
2.20.1
On Thu, 10 Oct 2019 at 02:05, Andrew Jeffery <[email protected]> wrote:
>
> The AST2500 has an explicit gate for the RMII RCLK for each of the two
> MACs.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <[email protected]> wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
On Thu, 10 Oct 2019 12:36:54 +1030, Andrew Jeffery wrote:
> The AST2500 has an explicit gate for the RMII RCLK for each of the two
> MACs.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
> ---
> v2: Drop "_GATE" from symbol names
>
> include/dt-bindings/clock/aspeed-clock.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
Hi Stephen,
On Thu, 10 Oct 2019 at 23:41, Joel Stanley <[email protected]> wrote:
>
> On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <[email protected]> wrote:
> >
> > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > single gate for each MAC.
> >
> > Signed-off-by: Andrew Jeffery <[email protected]>
>
> Reviewed-by: Joel Stanley <[email protected]>
I noticed this one hasn't been applied to clk-next.
Cheers,
Joel
Quoting Joel Stanley (2019-11-25 16:59:19)
> Hi Stephen,
>
> On Thu, 10 Oct 2019 at 23:41, Joel Stanley <[email protected]> wrote:
> >
> > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <[email protected]> wrote:
> > >
> > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > > single gate for each MAC.
> > >
> > > Signed-off-by: Andrew Jeffery <[email protected]>
> >
> > Reviewed-by: Joel Stanley <[email protected]>
>
> I noticed this one hasn't been applied to clk-next.
>
It's marked awaiting upstream in my UI. I think it was some patch that
might have come through your PR?
Quoting Andrew Jeffery (2019-10-09 19:06:55)
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery <[email protected]>
> ---
Applied to clk-next
On Tue, 26 Nov 2019 at 18:03, Stephen Boyd <[email protected]> wrote:
>
> Quoting Andrew Jeffery (2019-10-09 19:06:55)
> > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > single gate for each MAC.
> >
> > Signed-off-by: Andrew Jeffery <[email protected]>
> > ---
>
> Applied to clk-next
>
Thanks!