Add support for the Cadence QSPI controller. This controller is
present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
This driver has been tested on the Intel LGM SoCs.
This driver does not support generic SPI and also the implementation
only supports spi-mem interface to replace the existing driver in
mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR
flash memory.
v2 changes from v1:
Thank you Mark and Vignesh for the review comments and also shared link to develop
cadence-quadspi driver based on spi-mem framework against removal of legacy SPI.
Mark Brown Review comments:
If it's different versions of the same IP then everything should be in
one driver with the optional features enabled depending on what's in a
given system.
Vignesh review comments:
Nope, you cannot have two drivers for the same IP (i.e Cadence QSPI)
just to support to different types of SPI memories. This is the reason
why spi_mem_ops was introduced.
Please rewrite this driver over to use spi_mem_ops (instead of using
generic SPI xfers) so that same driver supports both SPI-NOR and
SPI-NAND flashes. Once that's done drivers/mtd/spi-nor/cadence-quadspi.c
can be deleted.
There are few existing examples of spi_mem_ops users in drivers/spi/
(git grep spi_mem_ops) and materials here on how to write such a driver:
[1] https://bootlin.com/blog/spi-mem-bringing-some-consistency-to-the-spi-memory-ecosystem/
[2] https://www.youtube.com/watch?v=PkWbuLM_gmU
Ramuthevar Vadivel Murugan (2):
dt-bindings: spi: Add schema for Cadence QSPI Controller driver
spi: cadence-quadpsi: Add support for the Cadence QSPI controller
.../devicetree/bindings/spi/cadence,qspi.yaml | 65 +
drivers/spi/Kconfig | 10 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-cadence-quadspi.c | 1290 ++++++++++++++++++++
drivers/spi/spi-cadence-quadspi.h | 272 +++++
5 files changed, 1638 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi.yaml
create mode 100644 drivers/spi/spi-cadence-quadspi.c
create mode 100644 drivers/spi/spi-cadence-quadspi.h
--
2.11.0
From: Ramuthevar Vadivel Murugan <[email protected]>
Add dt-bindings documentation for Cadence-QSPI controller to support
spi based flash memories.
Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
---
.../devicetree/bindings/spi/cadence,qspi.yaml | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi.yaml
diff --git a/Documentation/devicetree/bindings/spi/cadence,qspi.yaml b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
new file mode 100644
index 000000000000..295501f01e5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/cadence,qspi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence QSPI Flash Controller support
+
+maintainers:
+ - Ramuthevar Vadivel Murugan <[email protected]>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+description: |
+ Add support for the Cadence QSPI controller,This controller is
+ present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver
+ has been tested On Intel's LGM SoC.
+
+properties:
+ compatible:
+ const: cadence,qspi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clocks-names:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+examples:
+ - |
+ spi@ec000000 {
+ compatible = "cadence,qspi";
+ reg = <0xec000000 0x100>;
+ clocks = <&cgu0 LGM_CLK_QSPI>, <&cgu0 LGM_GCLK_QSPI>;
+ clock-names = "qspi";
+ resets = <&rcu0 0x10 1>;
+ reset-names = "qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash: flash@1 {
+ compatible = "spi-nand", "jedec, spi-nor";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+
--
2.11.0
Hi,
On 30/10/19 1:41 PM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <[email protected]>
>
> Add dt-bindings documentation for Cadence-QSPI controller to support
> spi based flash memories.
>
The new driver being added in patch 2/2 is supposed to replace
drivers/mtd/spi-nor/cadence-quadspi.c. Therefore the bindings should be
exactly same as
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt. Otherwise, it
breaks DT backward compatibility. There cannot be two different sets of
bindings for same HW IP.
Therefore please rewrite yaml schema to match existing bindings at
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt.
And then include a patch dropping older bindings.
> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
> ---
> .../devicetree/bindings/spi/cadence,qspi.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/cadence,qspi.yaml b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
> new file mode 100644
> index 000000000000..295501f01e5e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/cadence,qspi.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence QSPI Flash Controller support
> +
> +maintainers:
> + - Ramuthevar Vadivel Murugan <[email protected]>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +description: |
> + Add support for the Cadence QSPI controller,This controller is
> + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver
> + has been tested On Intel's LGM SoC.
> +
> +properties:
> + compatible:
> + const: cadence,qspi
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clocks-names:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> +
> +examples:
> + - |
> + spi@ec000000 {
> + compatible = "cadence,qspi";
> + reg = <0xec000000 0x100>;
> + clocks = <&cgu0 LGM_CLK_QSPI>, <&cgu0 LGM_GCLK_QSPI>;
> + clock-names = "qspi";
> + resets = <&rcu0 0x10 1>;
> + reset-names = "qspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash: flash@1 {
> + compatible = "spi-nand", "jedec, spi-nor";
s/"jedec, spi-nor"/"jedec,spi-nor" (i.e no space after comma)
> + reg = <1>;
> + spi-max-frequency = <10000000>;
> + };
> + };
> +
>
--
Regards
Vignesh
Hi Vignesh,
On 5/11/2019 12:30 PM, Vignesh Raghavendra wrote:
> Hi,
>
> On 30/10/19 1:41 PM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <[email protected]>
>>
>> Add dt-bindings documentation for Cadence-QSPI controller to support
>> spi based flash memories.
>>
> The new driver being added in patch 2/2 is supposed to replace
> drivers/mtd/spi-nor/cadence-quadspi.c. Therefore the bindings should be
> exactly same as
> Documentation/devicetree/bindings/mtd/cadence-quadspi.txt. Otherwise, it
> breaks DT backward compatibility. There cannot be two different sets of
> bindings for same HW IP.
>
> Therefore please rewrite yaml schema to match existing bindings at
> Documentation/devicetree/bindings/mtd/cadence-quadspi.txt.
> And then include a patch dropping older bindings.
sure, I will create dt-schema for the below file
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
---
With Best Regards
Vadivel
>
>> Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]>
>> ---
>> .../devicetree/bindings/spi/cadence,qspi.yaml | 65 ++++++++++++++++++++++
>> 1 file changed, 65 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/cadence,qspi.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/cadence,qspi.yaml b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
>> new file mode 100644
>> index 000000000000..295501f01e5e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/cadence,qspi.yaml
>> @@ -0,0 +1,65 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/spi/cadence,qspi.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Cadence QSPI Flash Controller support
>> +
>> +maintainers:
>> + - Ramuthevar Vadivel Murugan <[email protected]>
>> +
>> +allOf:
>> + - $ref: "spi-controller.yaml#"
>> +
>> +description: |
>> + Add support for the Cadence QSPI controller,This controller is
>> + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver
>> + has been tested On Intel's LGM SoC.
>> +
>> +properties:
>> + compatible:
>> + const: cadence,qspi
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clocks-names:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + reset-names:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> +
>> +examples:
>> + - |
>> + spi@ec000000 {
>> + compatible = "cadence,qspi";
>> + reg = <0xec000000 0x100>;
>> + clocks = <&cgu0 LGM_CLK_QSPI>, <&cgu0 LGM_GCLK_QSPI>;
>> + clock-names = "qspi";
>> + resets = <&rcu0 0x10 1>;
>> + reset-names = "qspi";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + flash: flash@1 {
>> + compatible = "spi-nand", "jedec, spi-nor";
> s/"jedec, spi-nor"/"jedec,spi-nor" (i.e no space after comma)
>
>> + reg = <1>;
>> + spi-max-frequency = <10000000>;
>> + };
>> + };
>> +
>>