The msm6242_set()/msm6242_clear() functions are used when writing to Control
Register D to set or clear the HOLD bit when reading the current time from
the RTC.
Doing this with a read-modify-write cycle will potentially clear an
interrupt condition which occurs between the read and the write.
The datasheet states the following about this:
When writing the HOLD or 30 second adjust bits of register D, it is
necessary to write the IRQ FLAG bit to a "1".
Since the only other bits in the register are the 30 second adjust bit
(which is not used) and the BUSY bit (which is read-only), the
read-modify-write cycle can be replaced by a simple write with the IRQ FLAG
bit set to 1 and the other bits (except HOLD) set to 0.
Cc: Geert Uytterhoeven <[email protected]>
Tested-by: Kars de Jong <[email protected]>
Signed-off-by: Kars de Jong <[email protected]>
---
drivers/rtc/rtc-msm6242.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/rtc/rtc-msm6242.c b/drivers/rtc/rtc-msm6242.c
index b1f2bedee77e..80e364baac53 100644
--- a/drivers/rtc/rtc-msm6242.c
+++ b/drivers/rtc/rtc-msm6242.c
@@ -88,28 +88,16 @@ static inline void msm6242_write(struct msm6242_priv *priv, unsigned int val,
__raw_writel(val, &priv->regs[reg]);
}
-static inline void msm6242_set(struct msm6242_priv *priv, unsigned int val,
- unsigned int reg)
-{
- msm6242_write(priv, msm6242_read(priv, reg) | val, reg);
-}
-
-static inline void msm6242_clear(struct msm6242_priv *priv, unsigned int val,
- unsigned int reg)
-{
- msm6242_write(priv, msm6242_read(priv, reg) & ~val, reg);
-}
-
static void msm6242_lock(struct msm6242_priv *priv)
{
int cnt = 5;
- msm6242_set(priv, MSM6242_CD_HOLD, MSM6242_CD);
+ msm6242_write(priv, MSM6242_CD_HOLD|MSM6242_CD_IRQ_FLAG, MSM6242_CD);
while ((msm6242_read(priv, MSM6242_CD) & MSM6242_CD_BUSY) && cnt) {
- msm6242_clear(priv, MSM6242_CD_HOLD, MSM6242_CD);
+ msm6242_write(priv, MSM6242_CD_IRQ_FLAG, MSM6242_CD);
udelay(70);
- msm6242_set(priv, MSM6242_CD_HOLD, MSM6242_CD);
+ msm6242_write(priv, MSM6242_CD_HOLD|MSM6242_CD_IRQ_FLAG, MSM6242_CD);
cnt--;
}
@@ -120,7 +108,7 @@ static void msm6242_lock(struct msm6242_priv *priv)
static void msm6242_unlock(struct msm6242_priv *priv)
{
- msm6242_clear(priv, MSM6242_CD_HOLD, MSM6242_CD);
+ msm6242_write(priv, MSM6242_CD_IRQ_FLAG, MSM6242_CD);
}
static int msm6242_read_time(struct device *dev, struct rtc_time *tm)
--
2.17.1
On 16/11/2019 12:46:20+0100, Kars de Jong wrote:
> The msm6242_set()/msm6242_clear() functions are used when writing to Control
> Register D to set or clear the HOLD bit when reading the current time from
> the RTC.
>
> Doing this with a read-modify-write cycle will potentially clear an
> interrupt condition which occurs between the read and the write.
>
> The datasheet states the following about this:
>
> When writing the HOLD or 30 second adjust bits of register D, it is
> necessary to write the IRQ FLAG bit to a "1".
>
> Since the only other bits in the register are the 30 second adjust bit
> (which is not used) and the BUSY bit (which is read-only), the
> read-modify-write cycle can be replaced by a simple write with the IRQ FLAG
> bit set to 1 and the other bits (except HOLD) set to 0.
>
> Cc: Geert Uytterhoeven <[email protected]>
> Tested-by: Kars de Jong <[email protected]>
> Signed-off-by: Kars de Jong <[email protected]>
> ---
> drivers/rtc/rtc-msm6242.c | 20 ++++----------------
> 1 file changed, 4 insertions(+), 16 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Sat, Nov 16, 2019 at 12:46 PM Kars de Jong <[email protected]> wrote:
> The msm6242_set()/msm6242_clear() functions are used when writing to Control
> Register D to set or clear the HOLD bit when reading the current time from
> the RTC.
>
> Doing this with a read-modify-write cycle will potentially clear an
> interrupt condition which occurs between the read and the write.
>
> The datasheet states the following about this:
>
> When writing the HOLD or 30 second adjust bits of register D, it is
> necessary to write the IRQ FLAG bit to a "1".
>
> Since the only other bits in the register are the 30 second adjust bit
> (which is not used) and the BUSY bit (which is read-only), the
> read-modify-write cycle can be replaced by a simple write with the IRQ FLAG
> bit set to 1 and the other bits (except HOLD) set to 0.
>
> Cc: Geert Uytterhoeven <[email protected]>
> Tested-by: Kars de Jong <[email protected]>
> Signed-off-by: Kars de Jong <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds