So far the HHI clock controller has been providing the XTAL clock on
Amlogic Meson8/Meson8b/Meson8m2 SoCs.
This is not correct because the XTAL is actually a crystal on the
boards and the SoC has a dedicated input for it.
This updates the dt-bindings of the HHI clock controller and defines
a fixed-clock in meson.dtsi (along with switching everything over to
use this clock).
The clock driver needs three updates to use this:
- patch #2 uses clk_hw_set_parent in the CPU clock notifier. This drops
the explicit reference to CLKID_XTAL while at the same time making
the code much easier (thanks to Neil for providing this new method
as part of the G12A CPU clock bringup!)
- patch #3 ensures that the clock driver doesn't rely on it's internal
XTAL clock while not losing support for older .dtbs that don't have
the XTAL clock input yet
- with patch #4 the clock controller's own XTAL clock is not registered
anymore when a clock input is provided via OF
This series is a functional no-op. It's main goal is to better represent
how the actual hardware looks like.
Changes since v2 at [1]:
- add .fw_name in addition to .name in patch #3 as suggested by Jerome
- dropped the dts patch so this whole series targets clk-meson
- moved patch #5 from another series to this one because once we drop
.name = "xtal" the clocks need to be aware of the OF node
Changes since v1 at [0]:
- add Rob's Reviewed-by to the dt-bindings patch
- check that "xtal" clock is actually passed via OF instead of checking
that there's any parent at all (which in the worst case may not be the
xtal clock) as suggested by Jerome
[0] https://patchwork.kernel.org/cover/11155515/
[1] https://patchwork.kernel.org/cover/11214189/
Martin Blumenstingl (5):
dt-bindings: clock: meson8b: add the clock inputs
clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
clk: meson: meson8b: change references to the XTAL clock to use
[fw_]name
clk: meson: meson8b: don't register the XTAL clock when provided via
OF
clk: meson: meson8b: use of_clk_hw_register to register the clocks
.../bindings/clock/amlogic,meson8b-clkc.txt | 5 +
drivers/clk/meson/meson8b.c | 113 ++++++++++--------
2 files changed, 67 insertions(+), 51 deletions(-)
--
2.24.0
The clock controller on Meson8/Meson8b/Meson8m2 has three (known)
inputs:
- "xtal": the main 24MHz crystal
- "ddr_pll": some of the audio clocks use the output of the DDR PLL as
input
- "clk_32k": an optional clock signal which can be connected to GPIOAO_6
(which then has to be switched to the CLK_32K_IN function)
Add the inputs to the documentation so we can wire up these inputs in a
follow-up patch.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Martin Blumenstingl <[email protected]>
---
.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
index 4d94091c1d2d..cc51e4746b3b 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt
@@ -11,6 +11,11 @@ Required Properties:
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
- #clock-cells: should be 1.
- #reset-cells: should be 1.
+- clocks: list of clock phandles, one for each entry in clock-names
+- clock-names: should contain the following:
+ * "xtal": the 24MHz system oscillator
+ * "ddr_pll": the DDR PLL clock
+ * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
Parent node should have the following properties :
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
--
2.24.0
Switch from clk_set_parent() to clk_hw_set_parent() now that we have a
way to configure a mux clock based on clk_hw pointers. This simplifies
the meson8b_cpu_clk_notifier_cb logic. No functional changes.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/meson8b.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 67e6691e080c..d376f80e806d 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -3585,7 +3585,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = {
struct meson8b_nb_data {
struct notifier_block nb;
- struct clk_hw_onecell_data *onecell_data;
+ struct clk_hw *cpu_clk;
};
static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
@@ -3593,30 +3593,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
{
struct meson8b_nb_data *nb_data =
container_of(nb, struct meson8b_nb_data, nb);
- struct clk_hw **hws = nb_data->onecell_data->hws;
- struct clk_hw *cpu_clk_hw, *parent_clk_hw;
- struct clk *cpu_clk, *parent_clk;
+ struct clk_hw *parent_clk;
int ret;
switch (event) {
case PRE_RATE_CHANGE:
- parent_clk_hw = hws[CLKID_XTAL];
+ /* xtal */
+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
break;
case POST_RATE_CHANGE:
- parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
+ /* cpu_scale_out_sel */
+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
break;
default:
return NOTIFY_DONE;
}
- cpu_clk_hw = hws[CLKID_CPUCLK];
- cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
-
- parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
-
- ret = clk_set_parent(cpu_clk, parent_clk);
+ ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
if (ret)
return notifier_from_errno(ret);
@@ -3695,7 +3690,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
return;
}
- meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
+ meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
/*
* FIXME we shouldn't program the muxes in notifier handlers. The
--
2.24.0
On Sun 17 Nov 2019 at 14:59, Martin Blumenstingl <[email protected]> wrote:
> So far the HHI clock controller has been providing the XTAL clock on
> Amlogic Meson8/Meson8b/Meson8m2 SoCs.
> This is not correct because the XTAL is actually a crystal on the
> boards and the SoC has a dedicated input for it.
>
> This updates the dt-bindings of the HHI clock controller and defines
> a fixed-clock in meson.dtsi (along with switching everything over to
> use this clock).
> The clock driver needs three updates to use this:
> - patch #2 uses clk_hw_set_parent in the CPU clock notifier. This drops
> the explicit reference to CLKID_XTAL while at the same time making
> the code much easier (thanks to Neil for providing this new method
> as part of the G12A CPU clock bringup!)
> - patch #3 ensures that the clock driver doesn't rely on it's internal
> XTAL clock while not losing support for older .dtbs that don't have
> the XTAL clock input yet
> - with patch #4 the clock controller's own XTAL clock is not registered
> anymore when a clock input is provided via OF
>
> This series is a functional no-op. It's main goal is to better represent
> how the actual hardware looks like.
>
>
> Changes since v2 at [1]:
> - add .fw_name in addition to .name in patch #3 as suggested by Jerome
> - dropped the dts patch so this whole series targets clk-meson
> - moved patch #5 from another series to this one because once we drop
> .name = "xtal" the clocks need to be aware of the OF node
>
> Changes since v1 at [0]:
> - add Rob's Reviewed-by to the dt-bindings patch
> - check that "xtal" clock is actually passed via OF instead of checking
> that there's any parent at all (which in the worst case may not be the
> xtal clock) as suggested by Jerome
>
>
> [0] https://patchwork.kernel.org/cover/11155515/
> [1] https://patchwork.kernel.org/cover/11214189/
>
>
> Martin Blumenstingl (5):
> dt-bindings: clock: meson8b: add the clock inputs
> clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
> clk: meson: meson8b: change references to the XTAL clock to use
> [fw_]name
> clk: meson: meson8b: don't register the XTAL clock when provided via
> OF
> clk: meson: meson8b: use of_clk_hw_register to register the clocks
>
> .../bindings/clock/amlogic,meson8b-clkc.txt | 5 +
> drivers/clk/meson/meson8b.c | 113 ++++++++++--------
> 2 files changed, 67 insertions(+), 51 deletions(-)
Applied for v5.6
Please note this will get rebased once v5.5-rc1 is out