The write-protect pin handling looks like a standard property that
could benefit other users if available in the core nvmem framework.
Instead of modifying all the drivers to check this pin, make the
nvmem subsystem check if the write-protect GPIO being passed
through the nvmem_config or defined in the device tree and pull it
low whenever writing to the memory.
This patchset:
- adds support for the write-protect pin split into two parts.
The first patch modifies modifies the relevant binding document,
while the second modifies the nvmem code to pull the write-protect
GPIO low (if present) during write operations.
- removes support for the write-protect pin split into two parts.
The first patch modifies the relevant binding document to remove
the wp-gpio, while the second removes the relevant code in the
at24 driver.
Changes since v1:
-Add an explenation on how the wp-gpios works
-keep reference to the wp-gpios in the at24 binding
Changes since v2:
-Use the flag GPIO_ACTIVE_HIGH instead of 0
Khouloud Touil (4):
dt-bindings: nvmem: new optional property write-protect-gpios
nvmem: add support for the write-protect pin
dt-bindings: at24: remove the optional property write-protect-gpios
eeprom: at24: remove the write-protect pin support
.../devicetree/bindings/eeprom/at24.yaml | 6 +-----
.../devicetree/bindings/nvmem/nvmem.yaml | 11 +++++++++++
drivers/misc/eeprom/at24.c | 9 ---------
drivers/nvmem/core.c | 19 +++++++++++++++++--
drivers/nvmem/nvmem.h | 2 ++
include/linux/nvmem-provider.h | 3 +++
6 files changed, 34 insertions(+), 16 deletions(-)
--
2.17.1
Several memories have a write-protect pin, that when pulled high, it
blocks the write operation.
On some boards, this pin is connected to a GPIO and pulled high by
default, which forces the user to manually change its state before
writing.
Instead of modifying all the memory drivers to check this pin, make
the NVMEM subsystem check if the write-protect GPIO being passed
through the nvmem_config or defined in the device tree and pull it
low whenever writing to the memory.
Add a new optional property to the device tree binding document, which
allows to specify the GPIO line to which the write-protect pin is
connected.
Signed-off-by: Khouloud Touil <[email protected]>
---
Documentation/devicetree/bindings/nvmem/nvmem.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
index 1c75a059206c..b43c6c65294e 100644
--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
@@ -34,6 +34,14 @@ properties:
description:
Mark the provider as read only.
+ wp-gpios:
+ description:
+ GPIO to which the write-protect pin of the chip is connected.
+ The write-protect GPIO is asserted, when it's driven high
+ (logical '1') to block the write operation. It's deasserted,
+ when it's driven low (logical '0') to allow writing.
+ maxItems: 1
+
patternProperties:
"^.*@[0-9a-f]+$":
type: object
@@ -63,9 +71,12 @@ patternProperties:
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
+
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
+ wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
/* ... */
--
2.17.1
On Thu, Dec 19, 2019 at 12:51:38PM +0100, Khouloud Touil wrote:
> Several memories have a write-protect pin, that when pulled high, it
> blocks the write operation.
Subject doesn't match the actual property name.
>
> On some boards, this pin is connected to a GPIO and pulled high by
> default, which forces the user to manually change its state before
> writing.
>
> Instead of modifying all the memory drivers to check this pin, make
> the NVMEM subsystem check if the write-protect GPIO being passed
> through the nvmem_config or defined in the device tree and pull it
> low whenever writing to the memory.
>
> Add a new optional property to the device tree binding document, which
> allows to specify the GPIO line to which the write-protect pin is
> connected.
>
> Signed-off-by: Khouloud Touil <[email protected]>
> ---
> Documentation/devicetree/bindings/nvmem/nvmem.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
> index 1c75a059206c..b43c6c65294e 100644
> --- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
> @@ -34,6 +34,14 @@ properties:
> description:
> Mark the provider as read only.
>
> + wp-gpios:
> + description:
> + GPIO to which the write-protect pin of the chip is connected.
> + The write-protect GPIO is asserted, when it's driven high
> + (logical '1') to block the write operation. It's deasserted,
> + when it's driven low (logical '0') to allow writing.
> + maxItems: 1
> +
> patternProperties:
> "^.*@[0-9a-f]+$":
> type: object
> @@ -63,9 +71,12 @@ patternProperties:
>
> examples:
> - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> qfprom: eeprom@700000 {
> #address-cells = <1>;
> #size-cells = <1>;
> + wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
>
> /* ... */
>
> --
> 2.17.1
>