From: Chen-Yu Tsai <[email protected]>
Hi everyone,
This is v2 of my A10/A20 CSI1 and R40 CSI0 series. v2 is simply the
remaining patches rebased on top of linux-next 20200106, with the
MBUS device tree binding changes converted to YAML format.
This series adds basic support for CSI1 on Allwinner A10/A20 and CSI0 on
Allwinner R40. The CSI1 block has the same structure and layout as the
CSI0 block. Differences include:
- Only one channel in BT.656 instead of four in CSI0
- 10-bit raw data input vs 8-bit in CSI0
- 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
- No ISP hardware (CSI SCLK not needed)
The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
in the A20. The register maps line up, and they support the same
features. The R40 appears to support BT.1120 based on the feature
overview, but it is not mentioned anywhere else. Also like the A20, the
ISP is not mentioned, but the CSI special clock needs to be enabled for
the hardware to function. The manual does state that the CSI special
clock is the TOP clock for all CSI hardware, but currently no hardware
exists for us to test if CSI1 also depends on it or not.
Included are a couple of fixes for signal polarity and DRAM offset
handling.
Patches 1 and 2 add CSI1 to A10 (sun4i) and A20 (sun7i) dtsi files.
Patch 3 adds a compatible string for the R40's MBUS (memory bus).
This patch needs to go through Rob's tree as it now depends on
the patch "dt-bindings: interconnect: Convert Allwinner MBUS
controller to a schema" that was already merged.
Patch 4 adds CSI0 to the R40 dtsi file
Patches 5 through 7 are examples of cameras hooked up to boards.
Regards
ChenYu
Chen-Yu Tsai (7):
ARM: dts: sun4i: Add CSI1 controller and pinmux options
ARM: dts: sun7i: Add CSI1 controller and pinmux options
dt-bindings: bus: sunxi: Add R40 MBUS compatible
ARM: dts: sun8i: r40: Add device node for CSI0
[DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on
CSI1
[DO NOT MERGE] ARM: dts: sun7i: cubieboard2: Enable OV7670 camera on
CSI1
[DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640
camera
.../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 1 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 42 ++++++++++++
arch/arm/boot/dts/sun4i-a10.dtsi | 35 ++++++++++
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 42 ++++++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 36 ++++++++++
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 67 +++++++++++++++++++
arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++
7 files changed, 259 insertions(+)
--
2.24.1
From: Chen-Yu Tsai <[email protected]>
Allwinner R40 SoC also contains MBUS controller.
Add compatible for it.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
Changes since v1:
- Reworked on top of "dt-bindings: interconnect: Convert Allwinner
MBUS controller to a schema"
This particular patch should go through Rob's tree, instead of the
sunxi tree.
---
.../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
index 9370e64992dd..23cda7437dcb 100644
--- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
@@ -30,6 +30,7 @@ properties:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
+ - allwinner,sun8i-r40-mbus
reg:
maxItems: 1
--
2.24.1
From: Chen-Yu Tsai <[email protected]>
The CSI controller driver now supports the second CSI controller, CSI1.
Add a device node for it. Pinmuxing options for the MCLK output, the
standard 8-bit interface, and a secondary 24-bit interface are included.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 35 ++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4c268b70b735..bf531efc0610 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -624,6 +624,16 @@ ohci1: usb@1c1c400 {
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <43>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -670,6 +680,31 @@ can0_ph_pins: can0-ph-pins {
function = "can";
};
+ /omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
emac_pins: emac0-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
--
2.24.1
On Mon, Jan 06, 2020 at 04:42:36PM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <[email protected]>
>
> Allwinner R40 SoC also contains MBUS controller.
>
> Add compatible for it.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Thanks!
Maxime
On Mon, Jan 06, 2020 at 04:42:33PM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <[email protected]>
>
> Hi everyone,
>
> This is v2 of my A10/A20 CSI1 and R40 CSI0 series. v2 is simply the
> remaining patches rebased on top of linux-next 20200106, with the
> MBUS device tree binding changes converted to YAML format.
>
> This series adds basic support for CSI1 on Allwinner A10/A20 and CSI0 on
> Allwinner R40. The CSI1 block has the same structure and layout as the
> CSI0 block. Differences include:
>
> - Only one channel in BT.656 instead of four in CSI0
> - 10-bit raw data input vs 8-bit in CSI0
> - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
> - No ISP hardware (CSI SCLK not needed)
>
> The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
> in the A20. The register maps line up, and they support the same
> features. The R40 appears to support BT.1120 based on the feature
> overview, but it is not mentioned anywhere else. Also like the A20, the
> ISP is not mentioned, but the CSI special clock needs to be enabled for
> the hardware to function. The manual does state that the CSI special
> clock is the TOP clock for all CSI hardware, but currently no hardware
> exists for us to test if CSI1 also depends on it or not.
>
> Included are a couple of fixes for signal polarity and DRAM offset
> handling.
>
> Patches 1 and 2 add CSI1 to A10 (sun4i) and A20 (sun7i) dtsi files.
>
> Patch 3 adds a compatible string for the R40's MBUS (memory bus).
> This patch needs to go through Rob's tree as it now depends on
> the patch "dt-bindings: interconnect: Convert Allwinner MBUS
> controller to a schema" that was already merged.
>
> Patch 4 adds CSI0 to the R40 dtsi file
>
> Patches 5 through 7 are examples of cameras hooked up to boards.
Applied 1,2 and 4, thanks!
Maxime
Hi Rob,
On Mon, Jan 6, 2020 at 4:52 PM Maxime Ripard <[email protected]> wrote:
>
> On Mon, Jan 06, 2020 at 04:42:36PM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <[email protected]>
> >
> > Allwinner R40 SoC also contains MBUS controller.
> >
> > Add compatible for it.
> >
> > Signed-off-by: Chen-Yu Tsai <[email protected]>
>
> Acked-by: Maxime Ripard <[email protected]>
Looks like this didn't get picked up. But the device tree change using
the new compatible did make it into v5.6-rc1.
Could you pick this up as a fix for v5.6 so they make the same release?
Or I could pick it through our tree.
Regards
ChenYu