This documents the devicetree bindings for the SDHC MMC host controller
found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a
bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including
HS200 mode (up to 100MHz clock). It embeds an internal clock controller
which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is
fed by four external input clocks (clkin[0-3]). "pclk" is the module
register clock, it has to be enabled to access the registers.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
.../bindings/mmc/amlogic,meson-mx-sdhc.yaml | 83 +++++++++++++++++++
.../dt-bindings/clock/meson-mx-sdhc-clkc.h | 8 ++
2 files changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
create mode 100644 include/dt-bindings/clock/meson-mx-sdhc-clkc.h
diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
new file mode 100644
index 000000000000..74632692ce26
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson SDHC controller Device Tree Bindings
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+maintainers:
+ - Martin Blumenstingl <[email protected]>
+
+description: |
+ The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
+ card interface with 1/4/8-bit bus width.
+ It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - amlogic,meson8-sdhc
+ - amlogic,meson8b-sdhc
+ - amlogic,meson8m2-sdhc
+ - const: amlogic,meson-mx-sdhc
+
+ reg:
+ minItems: 1
+
+ interrupts:
+ minItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ minItems: 9
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: mod_clk
+ - const: sd_clk
+ - const: rx_clk
+ - const: tx_clk
+ - const: clkin0
+ - const: clkin1
+ - const: clkin2
+ - const: clkin3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sdhc: mmc@8e00 {
+ compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
+ reg = <0x8e00 0x42>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ #clock-cells = <1>;
+ clocks = <&sdhc_pclk>,
+ <&sdhc SDHC_CLKID_MOD_CLK>,
+ <&sdhc SDHC_CLKID_SD_CLK>,
+ <&sdhc SDHC_CLKID_TX_CLK>,
+ <&sdhc SDHC_CLKID_RX_CLK>,
+ <&xtal>,
+ <&fclk_div4>,
+ <&fclk_div3>,
+ <&fclk_div5>;
+ clock-names = "pclk", "mod_clk", "sd_clk", "tx_clk", "rx_clk",
+ "clkin0", "clkin1", "clkin2", "clkin3";
+ };
diff --git a/include/dt-bindings/clock/meson-mx-sdhc-clkc.h b/include/dt-bindings/clock/meson-mx-sdhc-clkc.h
new file mode 100644
index 000000000000..ad9f6e4dc426
--- /dev/null
+++ b/include/dt-bindings/clock/meson-mx-sdhc-clkc.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#define SDHC_CLKID_SRC_SEL 0
+#define SDHC_CLKID_DIV 1
+#define SDHC_CLKID_MOD_CLK 2
+#define SDHC_CLKID_SD_CLK 3
+#define SDHC_CLKID_TX_CLK 4
+#define SDHC_CLKID_RX_CLK 5
--
2.24.1
On Sun, Jan 12, 2020 at 01:24:57AM +0100, Martin Blumenstingl wrote:
> This documents the devicetree bindings for the SDHC MMC host controller
> found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a
> bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including
> HS200 mode (up to 100MHz clock). It embeds an internal clock controller
> which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is
> fed by four external input clocks (clkin[0-3]). "pclk" is the module
> register clock, it has to be enabled to access the registers.
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> .../bindings/mmc/amlogic,meson-mx-sdhc.yaml | 83 +++++++++++++++++++
> .../dt-bindings/clock/meson-mx-sdhc-clkc.h | 8 ++
> 2 files changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
> create mode 100644 include/dt-bindings/clock/meson-mx-sdhc-clkc.h
Fails 'make dt_binding_check':
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.example.dts:17:53:
warning: extra tokens at end of #include directive
#include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
^
Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.example.dts:17:10:
fatal error: dt-bindings/clock/meson-mx-sdhc-clkc.yaml: No such file or directory
#include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
> new file mode 100644
> index 000000000000..74632692ce26
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic Meson SDHC controller Device Tree Bindings
> +
> +allOf:
> + - $ref: "mmc-controller.yaml"
> +
> +maintainers:
> + - Martin Blumenstingl <[email protected]>
> +
> +description: |
> + The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
> + card interface with 1/4/8-bit bus width.
> + It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - amlogic,meson8-sdhc
> + - amlogic,meson8b-sdhc
> + - amlogic,meson8m2-sdhc
> + - const: amlogic,meson-mx-sdhc
> +
> + reg:
> + minItems: 1
> +
> + interrupts:
> + minItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + minItems: 9
> +
> + clock-names:
> + items:
> + - const: pclk
> + - const: mod_clk
> + - const: sd_clk
> + - const: rx_clk
> + - const: tx_clk
> + - const: clkin0
> + - const: clkin1
> + - const: clkin2
> + - const: clkin3
Kind of odd to put the output clocks in the middle of the list.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#clock-cells"
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + sdhc: mmc@8e00 {
> + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
> + reg = <0x8e00 0x42>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
> + #clock-cells = <1>;
> + clocks = <&sdhc_pclk>,
> + <&sdhc SDHC_CLKID_MOD_CLK>,
> + <&sdhc SDHC_CLKID_SD_CLK>,
> + <&sdhc SDHC_CLKID_TX_CLK>,
> + <&sdhc SDHC_CLKID_RX_CLK>,
> + <&xtal>,
> + <&fclk_div4>,
> + <&fclk_div3>,
> + <&fclk_div5>;
> + clock-names = "pclk", "mod_clk", "sd_clk", "tx_clk", "rx_clk",
> + "clkin0", "clkin1", "clkin2", "clkin3";
> + };
> diff --git a/include/dt-bindings/clock/meson-mx-sdhc-clkc.h b/include/dt-bindings/clock/meson-mx-sdhc-clkc.h
> new file mode 100644
> index 000000000000..ad9f6e4dc426
> --- /dev/null
> +++ b/include/dt-bindings/clock/meson-mx-sdhc-clkc.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#define SDHC_CLKID_SRC_SEL 0
> +#define SDHC_CLKID_DIV 1
> +#define SDHC_CLKID_MOD_CLK 2
> +#define SDHC_CLKID_SD_CLK 3
> +#define SDHC_CLKID_TX_CLK 4
> +#define SDHC_CLKID_RX_CLK 5
> --
> 2.24.1
>
Hi Rob,
On Mon, Jan 13, 2020 at 10:10 PM Rob Herring <[email protected]> wrote:
>
> On Sun, Jan 12, 2020 at 01:24:57AM +0100, Martin Blumenstingl wrote:
> > This documents the devicetree bindings for the SDHC MMC host controller
> > found in Meson6, Meson8, Meson8b and Meson8m2 SoCs. It can use a
> > bus-width of 1/4/8-bit and it supports eMMC spec 4.4x/4.5x including
> > HS200 mode (up to 100MHz clock). It embeds an internal clock controller
> > which outputs four clocks (mod_clk, sd_clk, tx_clk and rx_clk) and is
> > fed by four external input clocks (clkin[0-3]). "pclk" is the module
> > register clock, it has to be enabled to access the registers.
> >
> > Signed-off-by: Martin Blumenstingl <[email protected]>
> > ---
> > .../bindings/mmc/amlogic,meson-mx-sdhc.yaml | 83 +++++++++++++++++++
> > .../dt-bindings/clock/meson-mx-sdhc-clkc.h | 8 ++
> > 2 files changed, 91 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.yaml
> > create mode 100644 include/dt-bindings/clock/meson-mx-sdhc-clkc.h
>
> Fails 'make dt_binding_check':
>
> Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.example.dts:17:53:
> warning: extra tokens at end of #include directive
> #include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
> ^
> Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdhc.example.dts:17:10:
> fatal error: dt-bindings/clock/meson-mx-sdhc-clkc.yaml: No such file or directory
> #include <dt-bindings/clock/meson-mx-sdhc-clkc.yaml>;
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
sorry for that - I'll fix it in v5
[...]
> > + clock-names:
> > + items:
> > + - const: pclk
> > + - const: mod_clk
> > + - const: sd_clk
> > + - const: rx_clk
> > + - const: tx_clk
> > + - const: clkin0
> > + - const: clkin1
> > + - const: clkin2
> > + - const: clkin3
>
> Kind of odd to put the output clocks in the middle of the list.
I'll have to re-send this anyways so I'll put clkin[0-3] at the start
of the list
Martin