This series add low power timer as boadcast clockevent device.
Low power timer could runs even when CPUs are in idle mode and
could wakeup them.
version 4:
- move defines in mfd/stm32-lptimer.h
- change compatible and subnode names
- document wakeup-source property
- reword commit message
- make driver Kconfig depends of MFD_STM32_LPTIMER
- remove useless include
- remove rate and clk fields from the private structure
- to add comments about the registers sequence in stm32_clkevent_lp_set_timer
- rework probe function and use devm_request_irq()
- do not allow module to be removed
version 3:
- fix timer set sequence
- don't forget to free irq on remove function
- use devm_kzalloc to simplify errors handling in probe function
version 2:
- stm32 clkevent driver is now a child of the stm32 lp timer node
- add a probe function and adpat the driver to use regmap provide
by it parent
- stop using timer_of helpers
Benjamin Gaignard (3):
dt-bindings: mfd: Document STM32 low power timer bindings
mfd: stm32: Add defines to be used for clkevent purpose
clocksource: Add Low Power STM32 timers driver
.../devicetree/bindings/mfd/st,stm32-lptimer.yaml | 16 ++
drivers/clocksource/Kconfig | 7 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-stm32-lp.c | 213 +++++++++++++++++++++
include/linux/mfd/stm32-lptimer.h | 5 +
5 files changed, 242 insertions(+)
create mode 100644 drivers/clocksource/timer-stm32-lp.c
--
2.15.0
Add defines to be able to enable/clear irq and configure one shot mode.
Signed-off-by: Benjamin Gaignard <[email protected]>
---
version 4:
- move defines in mfd/stm32-lptimer.h
include/linux/mfd/stm32-lptimer.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h
index 605f62264825..90b20550c1c8 100644
--- a/include/linux/mfd/stm32-lptimer.h
+++ b/include/linux/mfd/stm32-lptimer.h
@@ -27,10 +27,15 @@
#define STM32_LPTIM_CMPOK BIT(3)
/* STM32_LPTIM_ICR - bit fields */
+#define STM32_LPTIM_ARRMCF BIT(1)
#define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
+/* STM32_LPTIM_IER - bit flieds */
+#define STM32_LPTIM_ARRMIE BIT(1)
+
/* STM32_LPTIM_CR - bit fields */
#define STM32_LPTIM_CNTSTRT BIT(2)
+#define STM32_LPTIM_SNGSTRT BIT(1)
#define STM32_LPTIM_ENABLE BIT(0)
/* STM32_LPTIM_CFGR - bit fields */
--
2.15.0
Hi Lee,
On 17/02/2020 14:45, Benjamin Gaignard wrote:
> Add defines to be able to enable/clear irq and configure one shot mode.
>
> Signed-off-by: Benjamin Gaignard <[email protected]>
Are you fine if I pick this patch with the series?
> ---
> version 4:
> - move defines in mfd/stm32-lptimer.h
>
> include/linux/mfd/stm32-lptimer.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h
> index 605f62264825..90b20550c1c8 100644
> --- a/include/linux/mfd/stm32-lptimer.h
> +++ b/include/linux/mfd/stm32-lptimer.h
> @@ -27,10 +27,15 @@
> #define STM32_LPTIM_CMPOK BIT(3)
>
> /* STM32_LPTIM_ICR - bit fields */
> +#define STM32_LPTIM_ARRMCF BIT(1)
> #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
>
> +/* STM32_LPTIM_IER - bit flieds */
> +#define STM32_LPTIM_ARRMIE BIT(1)
> +
> /* STM32_LPTIM_CR - bit fields */
> #define STM32_LPTIM_CNTSTRT BIT(2)
> +#define STM32_LPTIM_SNGSTRT BIT(1)
> #define STM32_LPTIM_ENABLE BIT(0)
>
> /* STM32_LPTIM_CFGR - bit fields */
>
--
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On Thu, 20 Feb 2020, Daniel Lezcano wrote:
>
> Hi Lee,
>
> On 17/02/2020 14:45, Benjamin Gaignard wrote:
> > Add defines to be able to enable/clear irq and configure one shot mode.
> >
> > Signed-off-by: Benjamin Gaignard <[email protected]>
>
> Are you fine if I pick this patch with the series?
Acked-by: Lee Jones <[email protected]>
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Thu, 20 Feb 2020, Daniel Lezcano wrote:
> On 17/02/2020 14:45, Benjamin Gaignard wrote:
> > Add defines to be able to enable/clear irq and configure one shot mode.
> >
> > Signed-off-by: Benjamin Gaignard <[email protected]>
>
> Are you fine if I pick this patch with the series?
Nothing heard from you since I Acked this.
Are you still planning on taking this patch?
If so, can you also take patch 1 please?
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On 3/19/20 11:10 AM, Lee Jones wrote:
> On Thu, 20 Feb 2020, Daniel Lezcano wrote:
>> On 17/02/2020 14:45, Benjamin Gaignard wrote:
>>> Add defines to be able to enable/clear irq and configure one shot mode.
>>>
>>> Signed-off-by: Benjamin Gaignard <[email protected]>
>> Are you fine if I pick this patch with the series?
> Nothing heard from you since I Acked this.
>
> Are you still planning on taking this patch?
>
> If so, can you also take patch 1 please?
I will send a v5.
Daniel could you wait until that to merge all the patches (even if this
one won't change) ?
Benjamin
>
On 19/03/2020 11:28, Benjamin GAIGNARD wrote:
>
>
> On 3/19/20 11:10 AM, Lee Jones wrote:
>> On Thu, 20 Feb 2020, Daniel Lezcano wrote:
>>> On 17/02/2020 14:45, Benjamin Gaignard wrote:
>>>> Add defines to be able to enable/clear irq and configure one shot mode.
>>>>
>>>> Signed-off-by: Benjamin Gaignard <[email protected]>
>>> Are you fine if I pick this patch with the series?
>> Nothing heard from you since I Acked this.
>>
>> Are you still planning on taking this patch?
>>
>> If so, can you also take patch 1 please?
> I will send a v5.
> Daniel could you wait until that to merge all the patches (even if this
> one won't change) ?
Sure, no problem.
--
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