Amlogic uses a proprietary lossless image compression protocol and format
for their hardware video codec accelerators, either video decoders or
video input encoders.
It considerably reduces memory bandwidth while writing and reading
frames in memory.
The underlying storage is considered to be 3 components, 8bit or 10-bit
per component, YCbCr 420, single plane :
- DRM_FORMAT_YUV420_8BIT
- DRM_FORMAT_YUV420_10BIT
This modifier will be notably added to DMA-BUF frames imported from the V4L2
Amlogic VDEC decoder.
At least two options are supported :
- Scatter mode: the buffer is filled with a IOMMU scatter table referring
to the encoder current memory layout. This mode if more efficient in terms
of memory allocation but frames are not dumpable and only valid during until
the buffer is freed and back in control of the encoder
- Memory saving: when the pixel bpp is 8b, the size of the superblock can
be reduced, thus saving memory.
This serie adds the missing register, updated the FBC decoder registers
content to be committed by the crtc code.
The Amlogic FBC has been tested with compressed content from the Amlogic
HW VP9 decoder on S905X (GXL), S905D2 (G12A) and S905X3 (SM1) in 8bit
(Scatter+Mem Saving on G12A/SM1, Mem Saving on GXL) and 10bit
(Scatter on G12A/SM1, default on GXL).
It's expected to work as-is on GXM and G12B SoCs.
Neil Armstrong (4):
drm/fourcc: Add modifier definitions for describing Amlogic Video
Framebuffer Compression
drm/meson: add Amlogic Video FBC registers
drm/meson: overlay: setup overlay for Amlogic FBC
drm/meson: crtc: handle commit of Amlogic FBC frames
drivers/gpu/drm/meson/meson_crtc.c | 118 ++++++++---
drivers/gpu/drm/meson/meson_drv.h | 16 ++
drivers/gpu/drm/meson/meson_overlay.c | 257 +++++++++++++++++++++++-
drivers/gpu/drm/meson/meson_registers.h | 22 ++
include/uapi/drm/drm_fourcc.h | 56 ++++++
5 files changed, 431 insertions(+), 38 deletions(-)
--
2.22.0
Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing
register.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 8ea00546cd4e..f784d7d1fe2e 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -144,10 +144,15 @@
#define VIU_SW_RESET_OSD1 BIT(0)
#define VIU_MISC_CTRL0 0x1a06
#define VIU_CTRL0_VD1_AFBC_MASK 0x170000
+#define VIU_CTRL0_AFBC_TO_VD1 BIT(20)
#define VIU_MISC_CTRL1 0x1a07
#define MALI_AFBC_MISC GENMASK(15, 8)
#define D2D3_INTF_LENGTH 0x1a08
#define D2D3_INTF_CTRL0 0x1a09
+#define VD1_AFBCD0_MISC_CTRL 0x1a0a
+#define VD1_AXI_SEL_AFB (1 << 12)
+#define AFBC_VD1_SEL (1 << 10)
+#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define VIU_OSD1_CTRL_STAT 0x1a10
#define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
#define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)
@@ -365,6 +370,23 @@
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
#define AFBC_ENABLE 0x1ae0
+#define AFBC_MODE 0x1ae1
+#define AFBC_SIZE_IN 0x1ae2
+#define AFBC_DEC_DEF_COLOR 0x1ae3
+#define AFBC_CONV_CTRL 0x1ae4
+#define AFBC_LBUF_DEPTH 0x1ae5
+#define AFBC_HEAD_BADDR 0x1ae6
+#define AFBC_BODY_BADDR 0x1ae7
+#define AFBC_SIZE_OUT 0x1ae8
+#define AFBC_OUT_YSCOPE 0x1ae9
+#define AFBC_STAT 0x1aea
+#define AFBC_VD_CFMT_CTRL 0x1aeb
+#define AFBC_VD_CFMT_W 0x1aec
+#define AFBC_MIF_HOR_SCOPE 0x1aed
+#define AFBC_MIF_VER_SCOPE 0x1aee
+#define AFBC_PIXEL_HOR_SCOPE 0x1aef
+#define AFBC_PIXEL_VER_SCOPE 0x1af0
+#define AFBC_VD_CFMT_H 0x1af1
/* vpp */
#define VPP_DUMMY_DATA 0x1d00
--
2.22.0
Le 20/02/2020 ? 17:27, Neil Armstrong a ?crit :
> Add the registers of the VPU VD1 Amlogic FBC decoder module, and routing
> register.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/gpu/drm/meson/meson_registers.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
> index 8ea00546cd4e..f784d7d1fe2e 100644
> --- a/drivers/gpu/drm/meson/meson_registers.h
> +++ b/drivers/gpu/drm/meson/meson_registers.h
> @@ -144,10 +144,15 @@
> #define VIU_SW_RESET_OSD1 BIT(0)
> #define VIU_MISC_CTRL0 0x1a06
> #define VIU_CTRL0_VD1_AFBC_MASK 0x170000
> +#define VIU_CTRL0_AFBC_TO_VD1 BIT(20)
> #define VIU_MISC_CTRL1 0x1a07
> #define MALI_AFBC_MISC GENMASK(15, 8)
> #define D2D3_INTF_LENGTH 0x1a08
> #define D2D3_INTF_CTRL0 0x1a09
> +#define VD1_AFBCD0_MISC_CTRL 0x1a0a
> +#define VD1_AXI_SEL_AFB (1 << 12)
---------------------------------------/\
Missing 'C'
Thanks Christian for reporting.... last minute checkpatch fix gone wrong.
Will fix either in v2 or when applying.
Neil
> +#define AFBC_VD1_SEL (1 << 10)
> +#define VD2_AFBCD1_MISC_CTRL 0x1a0b
> #define VIU_OSD1_CTRL_STAT 0x1a10
> #define VIU_OSD1_OSD_BLK_ENABLE BIT(0)
> #define VIU_OSD1_OSD_MEM_MODE_LINEAR BIT(2)
> @@ -365,6 +370,23 @@
> #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
> #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
> #define AFBC_ENABLE 0x1ae0
> +#define AFBC_MODE 0x1ae1
> +#define AFBC_SIZE_IN 0x1ae2
> +#define AFBC_DEC_DEF_COLOR 0x1ae3
> +#define AFBC_CONV_CTRL 0x1ae4
> +#define AFBC_LBUF_DEPTH 0x1ae5
> +#define AFBC_HEAD_BADDR 0x1ae6
> +#define AFBC_BODY_BADDR 0x1ae7
> +#define AFBC_SIZE_OUT 0x1ae8
> +#define AFBC_OUT_YSCOPE 0x1ae9
> +#define AFBC_STAT 0x1aea
> +#define AFBC_VD_CFMT_CTRL 0x1aeb
> +#define AFBC_VD_CFMT_W 0x1aec
> +#define AFBC_MIF_HOR_SCOPE 0x1aed
> +#define AFBC_MIF_VER_SCOPE 0x1aee
> +#define AFBC_PIXEL_HOR_SCOPE 0x1aef
> +#define AFBC_PIXEL_VER_SCOPE 0x1af0
> +#define AFBC_VD_CFMT_H 0x1af1
>
> /* vpp */
> #define VPP_DUMMY_DATA 0x1d00
>
Neil Armstrong <[email protected]> writes:
> Amlogic uses a proprietary lossless image compression protocol and format
> for their hardware video codec accelerators, either video decoders or
> video input encoders.
>
> It considerably reduces memory bandwidth while writing and reading
> frames in memory.
>
> The underlying storage is considered to be 3 components, 8bit or 10-bit
> per component, YCbCr 420, single plane :
> - DRM_FORMAT_YUV420_8BIT
> - DRM_FORMAT_YUV420_10BIT
>
> This modifier will be notably added to DMA-BUF frames imported from the V4L2
> Amlogic VDEC decoder.
>
> At least two options are supported :
> - Scatter mode: the buffer is filled with a IOMMU scatter table referring
> to the encoder current memory layout. This mode if more efficient in terms
> of memory allocation but frames are not dumpable and only valid during until
> the buffer is freed and back in control of the encoder
> - Memory saving: when the pixel bpp is 8b, the size of the superblock can
> be reduced, thus saving memory.
>
> This serie adds the missing register, updated the FBC decoder registers
> content to be committed by the crtc code.
>
> The Amlogic FBC has been tested with compressed content from the Amlogic
> HW VP9 decoder on S905X (GXL), S905D2 (G12A) and S905X3 (SM1) in 8bit
> (Scatter+Mem Saving on G12A/SM1, Mem Saving on GXL) and 10bit
> (Scatter on G12A/SM1, default on GXL).
>
> It's expected to work as-is on GXM and G12B SoCs.
Tested on meson-sm1-sei610 with 4k@60p (VP9) streams.
Tested-by: Kevin Hilman <[email protected]>
Kevin