From: Peng Fan <[email protected]>
Use nvmem API is better compared with direclty accessing OCOTP registers.
nvmem could handle OCOTP clk, defer probe.
Patch 1/3 is dts changes to add nvmem related properties
Patch 2/3 is a bug fix
Patch 3/3 is convert to nvmem API
Peng Fan (3):
ARM: dts: imx: add nvmem property for cpu0
cpufreq: imx6q: fix error handling
cpufreq: imx6q: read OCOTP through nvmem for imx6q
arch/arm/boot/dts/imx6dl.dtsi | 2 ++
arch/arm/boot/dts/imx6q.dtsi | 2 ++
arch/arm/boot/dts/imx6qdl.dtsi | 7 ++++
arch/arm/boot/dts/imx6sl.dtsi | 9 ++++++
arch/arm/boot/dts/imx6sll.dtsi | 6 ++++
arch/arm/boot/dts/imx6sx.dtsi | 6 ++++
drivers/cpufreq/imx6q-cpufreq.c | 72 +++++++++++++++++++++++------------------
7 files changed, 73 insertions(+), 31 deletions(-)
--
2.16.4
From: Peng Fan <[email protected]>
Add nvmem related property for cpu0, then nvmem API could be used
to read cpu speed grading to avoid directly read OCOTP registers
mapped which could not handle defer probe.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm/boot/dts/imx6dl.dtsi | 2 ++
arch/arm/boot/dts/imx6q.dtsi | 2 ++
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
arch/arm/boot/dts/imx6sl.dtsi | 9 +++++++++
arch/arm/boot/dts/imx6sll.dtsi | 6 ++++++
arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++
6 files changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 4b3a128d9260..055f1d875bac 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -44,6 +44,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
cpu@1 {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 0fad13f9d336..d3ba9d4a1290 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -49,6 +49,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 70fb8b56b1d7..982f546b0b89 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1165,6 +1165,13 @@
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6QDL_CLK_IIM>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
tzasc@21d0000 { /* TZASC1 */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c8ec46fe8302..de943341e4f2 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -74,6 +74,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -953,6 +955,13 @@
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
audmux: audmux@21d8000 {
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 797f850492fe..6b7fb3cec9f6 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -72,6 +72,8 @@
<&clks IMX6SLL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -791,6 +793,10 @@
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SLL_CLK_OCOTP>;
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index e47d346a3543..63aa19d81b42 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -87,6 +87,8 @@
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -1058,6 +1060,10 @@
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
--
2.16.4
From: Peng Fan <[email protected]>
When speed checking failed, direclty jumping to put_node label
is not correct. Need jump to out_free_opp to avoid resources leak.
Fixes: 2733fb0d0699 ("cpufreq: imx6q: read OCOTP through nvmem for imx6ul/imx6ull")
Signed-off-by: Peng Fan <[email protected]>
---
drivers/cpufreq/imx6q-cpufreq.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 648a09a1778a..b634a73d1f8f 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -378,23 +378,24 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
goto put_reg;
}
+ /* Because we have added the OPPs here, we must free them */
+ free_opp = true;
+
if (of_machine_is_compatible("fsl,imx6ul") ||
of_machine_is_compatible("fsl,imx6ull")) {
ret = imx6ul_opp_check_speed_grading(cpu_dev);
if (ret) {
if (ret == -EPROBE_DEFER)
- goto put_node;
+ goto out_free_opp;
dev_err(cpu_dev, "failed to read ocotp: %d\n",
ret);
- goto put_node;
+ goto out_free_opp;
}
} else {
imx6q_opp_check_speed_grading(cpu_dev);
}
- /* Because we have added the OPPs here, we must free them */
- free_opp = true;
num = dev_pm_opp_get_opp_count(cpu_dev);
if (num < 0) {
ret = num;
--
2.16.4
From: Peng Fan <[email protected]>
Directly accessing OCOTP registers should be avoided, because
it could not handle OCOTP clks and could not handle defer
proper. With nvmem API, it is safe to access OCOTP registers.
To make sure old dtb could work, the original code still kept.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/cpufreq/imx6q-cpufreq.c | 67 +++++++++++++++++++++++------------------
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index b634a73d1f8f..183c03a44187 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -216,31 +216,41 @@ static struct cpufreq_driver imx6q_cpufreq_driver = {
#define OCOTP_CFG3_SPEED_996MHZ 0x2
#define OCOTP_CFG3_SPEED_852MHZ 0x1
-static void imx6q_opp_check_speed_grading(struct device *dev)
+static int imx6q_opp_check_speed_grading(struct device *dev)
{
struct device_node *np;
void __iomem *base;
u32 val;
+ int ret;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
- if (!np)
- return;
+ if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
+ ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
+ if (ret)
+ return ret;
+ } else {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
+ if (!np)
+ return -ENOENT;
- base = of_iomap(np, 0);
- if (!base) {
- dev_err(dev, "failed to map ocotp\n");
- goto put_node;
+ base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!base) {
+ dev_err(dev, "failed to map ocotp\n");
+ return -EFAULT;
+ }
+
+ /*
+ * SPEED_GRADING[1:0] defines the max speed of ARM:
+ * 2b'11: 1200000000Hz;
+ * 2b'10: 996000000Hz;
+ * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
+ * 2b'00: 792000000Hz;
+ * We need to set the max speed of ARM according to fuse map.
+ */
+ val = readl_relaxed(base + OCOTP_CFG3);
+ iounmap(base);
}
- /*
- * SPEED_GRADING[1:0] defines the max speed of ARM:
- * 2b'11: 1200000000Hz;
- * 2b'10: 996000000Hz;
- * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
- * 2b'00: 792000000Hz;
- * We need to set the max speed of ARM according to fuse map.
- */
- val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
@@ -257,9 +267,8 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
if (dev_pm_opp_disable(dev, 1200000000))
dev_warn(dev, "failed to disable 1.2GHz OPP\n");
}
- iounmap(base);
-put_node:
- of_node_put(np);
+
+ return 0;
}
#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
@@ -384,16 +393,16 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
if (of_machine_is_compatible("fsl,imx6ul") ||
of_machine_is_compatible("fsl,imx6ull")) {
ret = imx6ul_opp_check_speed_grading(cpu_dev);
- if (ret) {
- if (ret == -EPROBE_DEFER)
- goto out_free_opp;
-
- dev_err(cpu_dev, "failed to read ocotp: %d\n",
- ret);
- goto out_free_opp;
- }
} else {
- imx6q_opp_check_speed_grading(cpu_dev);
+ ret = imx6q_opp_check_speed_grading(cpu_dev);
+ }
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ goto out_free_opp;
+
+ dev_err(cpu_dev, "failed to read ocotp: %d\n",
+ ret);
+ goto out_free_opp;
}
num = dev_pm_opp_get_opp_count(cpu_dev);
--
2.16.4
On 03-03-20, 10:14, [email protected] wrote:
> From: Peng Fan <[email protected]>
>
> Use nvmem API is better compared with direclty accessing OCOTP registers.
> nvmem could handle OCOTP clk, defer probe.
>
> Patch 1/3 is dts changes to add nvmem related properties
> Patch 2/3 is a bug fix
> Patch 3/3 is convert to nvmem API
Should I apply patch 2 and 3 ? And you can take 1/3 via ARM Soc tree
as this shouldn't break anything.
--
viresh
Hi Viresh,
> Subject: Re: [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API
>
> On 03-03-20, 10:14, [email protected] wrote:
> > From: Peng Fan <[email protected]>
> >
> > Use nvmem API is better compared with direclty accessing OCOTP registers.
> > nvmem could handle OCOTP clk, defer probe.
> >
> > Patch 1/3 is dts changes to add nvmem related properties Patch 2/3 is
> > a bug fix Patch 3/3 is convert to nvmem API
>
> Should I apply patch 2 and 3 ? And you can take 1/3 via ARM Soc tree as this
> shouldn't break anything.
Please take patch 2 and 3. Without patch 1, it just use legacy method,
not break things.
Thanks,
Peng.
>
> --
> viresh
On 03-03-20, 06:16, Peng Fan wrote:
> Hi Viresh,
>
> > Subject: Re: [PATCH 0/3] Convert i.MX6Q cpufreq to use nvmem API
> >
> > On 03-03-20, 10:14, [email protected] wrote:
> > > From: Peng Fan <[email protected]>
> > >
> > > Use nvmem API is better compared with direclty accessing OCOTP registers.
> > > nvmem could handle OCOTP clk, defer probe.
> > >
> > > Patch 1/3 is dts changes to add nvmem related properties Patch 2/3 is
> > > a bug fix Patch 3/3 is convert to nvmem API
> >
> > Should I apply patch 2 and 3 ? And you can take 1/3 via ARM Soc tree as this
> > shouldn't break anything.
>
> Please take patch 2 and 3. Without patch 1, it just use legacy method,
> not break things.
Applied. Thanks.
--
viresh
On Tue, Mar 03, 2020 at 10:14:48AM +0800, [email protected] wrote:
> From: Peng Fan <[email protected]>
>
> Add nvmem related property for cpu0, then nvmem API could be used
> to read cpu speed grading to avoid directly read OCOTP registers
> mapped which could not handle defer probe.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm/boot/dts/imx6dl.dtsi | 2 ++
> arch/arm/boot/dts/imx6q.dtsi | 2 ++
> arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
> arch/arm/boot/dts/imx6sl.dtsi | 9 +++++++++
> arch/arm/boot/dts/imx6sll.dtsi | 6 ++++++
> arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++
> 6 files changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
> index 4b3a128d9260..055f1d875bac 100644
> --- a/arch/arm/boot/dts/imx6dl.dtsi
> +++ b/arch/arm/boot/dts/imx6dl.dtsi
> @@ -44,6 +44,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
>
> cpu@1 {
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 0fad13f9d336..d3ba9d4a1290 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -49,6 +49,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
>
> cpu1: cpu@1 {
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 70fb8b56b1d7..982f546b0b89 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -1165,6 +1165,13 @@
> compatible = "fsl,imx6q-ocotp", "syscon";
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6QDL_CLK_IIM>;
> +
Please drop such newline. Do not really think they are necessary.
Shawn
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> };
>
> tzasc@21d0000 { /* TZASC1 */
> diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
> index c8ec46fe8302..de943341e4f2 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -74,6 +74,8 @@
> arm-supply = <®_arm>;
> pu-supply = <®_pu>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -953,6 +955,13 @@
> compatible = "fsl,imx6sl-ocotp", "syscon";
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SL_CLK_OCOTP>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> };
>
> audmux: audmux@21d8000 {
> diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
> index 797f850492fe..6b7fb3cec9f6 100644
> --- a/arch/arm/boot/dts/imx6sll.dtsi
> +++ b/arch/arm/boot/dts/imx6sll.dtsi
> @@ -72,6 +72,8 @@
> <&clks IMX6SLL_CLK_PLL1_SYS>;
> clock-names = "arm", "pll2_pfd2_396m", "step",
> "pll1_sw", "pll1_sys";
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -791,6 +793,10 @@
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SLL_CLK_OCOTP>;
>
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> +
> tempmon_calib: calib@38 {
> reg = <0x38 4>;
> };
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index e47d346a3543..63aa19d81b42 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -87,6 +87,8 @@
> "pll1_sw", "pll1_sys";
> arm-supply = <®_arm>;
> soc-supply = <®_soc>;
> + nvmem-cells = <&cpu_speed_grade>;
> + nvmem-cell-names = "speed_grade";
> };
> };
>
> @@ -1058,6 +1060,10 @@
> reg = <0x021bc000 0x4000>;
> clocks = <&clks IMX6SX_CLK_OCOTP>;
>
> + cpu_speed_grade: speed-grade@10 {
> + reg = <0x10 4>;
> + };
> +
> tempmon_calib: calib@38 {
> reg = <0x38 4>;
> };
> --
> 2.16.4
>