The Allwinner F1C100s has an MUSB-based USB peripheral. This patch
series implements support for it alongside existing Allwinner support
code.
This series was originally written by Icenowy Zheng for Linux v4.14.
I've rebased and bugfixed that work against mainline and tested it on
both the Lichee Nano and my custom hardware.
This resubmit is unchanged from the series I sent a couple weeks ago,
although I've expanded the Cc: to the linux-usb list.
George Hilliard (3):
dt-bindings: Add new F1C100s compatible strings for USB
phy: sun4i-usb: add support for the USB PHY on suniv SoC
musb: sunxi: add support for the suniv MUSB controller
Icenowy Zheng (2):
ARM: suniv: add USB-related device nodes
ARM: suniv: f1c100s: enable USB on Lichee Pi Nano
.../phy/allwinner,sun4i-a10-usb-phy.yaml | 1 +
.../usb/allwinner,sun4i-a10-musb.yaml | 1 +
.../boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++
arch/arm/boot/dts/suniv-f1c100s.dtsi | 29 +++++++++++++++++++
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++
drivers/usb/musb/sunxi.c | 8 +++--
6 files changed, 64 insertions(+), 2 deletions(-)
--
2.25.0
The suniv SoC has one USB OTG port connected to a MUSB controller.
Add support for its USB PHY.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: George Hilliard <[email protected]>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 856927382248..5fb0c42fe8fd 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -98,6 +98,7 @@
#define POLL_TIME msecs_to_jiffies(250)
enum sun4i_usb_phy_type {
+ suniv_f1c100s_phy,
sun4i_a10_phy,
sun6i_a31_phy,
sun8i_a33_phy,
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
+ .num_phys = 1,
+ .type = suniv_f1c100s_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A10,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3,
.type = sun4i_a10_phy,
@@ -973,6 +982,8 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
};
static const struct of_device_id sun4i_usb_phy_of_match[] = {
+ { .compatible = "allwinner,suniv-f1c100s-usb-phy",
+ .data = &suniv_f1c100s_cfg },
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
--
2.25.0
The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
region to be claimed.
Add support for it.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: George Hilliard <[email protected]>
---
drivers/usb/musb/sunxi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index f3f76f2ac63f..76806b781844 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -714,14 +714,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
INIT_WORK(&glue->work, sunxi_musb_work);
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
- if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+ }
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
- of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+ of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
}
@@ -814,6 +817,7 @@ static int sunxi_musb_remove(struct platform_device *pdev)
}
static const struct of_device_id sunxi_musb_match[] = {
+ { .compatible = "allwinner,suniv-f1c100s-musb", },
{ .compatible = "allwinner,sun4i-a10-musb", },
{ .compatible = "allwinner,sun6i-a31-musb", },
{ .compatible = "allwinner,sun8i-a33-musb", },
--
2.25.0
From: Icenowy Zheng <[email protected]>
Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected
to the USB pins of the SoC and ID pin connected to PE2 GPIO.
Enable the USB functionality.
This patch depends on the previous change to the F1C100s device tree.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: George Hilliard <[email protected]>
---
.../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6c7cb5..c42186e22d45 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -19,8 +21,22 @@ chosen {
};
};
+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
--
2.25.0
From: Icenowy Zheng <[email protected]>
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: George Hilliard <[email protected]>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b75f61..ec9f248ba889 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
* Copyright 2018 Mesih Kilinc <[email protected]>
*/
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -140,5 +143,31 @@ uart2: serial@1c25800 {
resets = <&ccu 26>;
status = "disabled";
};
+
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
};
};
--
2.25.0
On Tue, Mar 10, 2020 at 4:43 AM George Hilliard
<[email protected]> wrote:
>
> The suniv SoC has one USB OTG port connected to a MUSB controller.
>
> Add support for its USB PHY.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
Not sure why Icenowy's SoB is here. If she was the original author, you
are supposed to keep her name as the author.
> Signed-off-by: George Hilliard <[email protected]>
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 856927382248..5fb0c42fe8fd 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -98,6 +98,7 @@
> #define POLL_TIME msecs_to_jiffies(250)
>
> enum sun4i_usb_phy_type {
> + suniv_f1c100s_phy,
> sun4i_a10_phy,
> sun6i_a31_phy,
> sun8i_a33_phy,
> @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> + .num_phys = 1,
> + .type = suniv_f1c100s_phy,
> + .disc_thresh = 3,
> + .phyctl_offset = REG_PHYCTL_A10,
> + .dedicated_clocks = true,
> +};
> +
> static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> .num_phys = 3,
> .type = sun4i_a10_phy,
> @@ -973,6 +982,8 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
> };
>
> static const struct of_device_id sun4i_usb_phy_of_match[] = {
> + { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> + .data = &suniv_f1c100s_cfg },
> { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
Please use the same style (and ignore checkpatch.pl on this one).
ChenYu
> { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
> { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
> --
> 2.25.0
>
On Thu, Mar 12, 2020 at 2:51 PM Chen-Yu Tsai <[email protected]> wrote:
>
> On Tue, Mar 10, 2020 at 4:43 AM George Hilliard
> <[email protected]> wrote:
> >
> > The suniv SoC has one USB OTG port connected to a MUSB controller.
> >
> > Add support for its USB PHY.
> >
> > Signed-off-by: Icenowy Zheng <[email protected]>
>
> Not sure why Icenowy's SoB is here. If she was the original author, you
> are supposed to keep her name as the author.
>
> > Signed-off-by: George Hilliard <[email protected]>
> > ---
> > drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
> > index 856927382248..5fb0c42fe8fd 100644
> > --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> > @@ -98,6 +98,7 @@
> > #define POLL_TIME msecs_to_jiffies(250)
> >
> > enum sun4i_usb_phy_type {
> > + suniv_f1c100s_phy,
> > sun4i_a10_phy,
> > sun6i_a31_phy,
> > sun8i_a33_phy,
> > @@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
> > return 0;
> > }
> >
> > +static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
> > + .num_phys = 1,
> > + .type = suniv_f1c100s_phy,
> > + .disc_thresh = 3,
> > + .phyctl_offset = REG_PHYCTL_A10,
> > + .dedicated_clocks = true,
> > +};
> > +
> > static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> > .num_phys = 3,
> > .type = sun4i_a10_phy,
> > @@ -973,6 +982,8 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
> > };
> >
> > static const struct of_device_id sun4i_usb_phy_of_match[] = {
> > + { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > + .data = &suniv_f1c100s_cfg },
> > { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
>
> Please use the same style (and ignore checkpatch.pl on this one).
>
> ChenYu
>
> > { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
> > { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
Also, please stick to the same ordering in the driver and the bindings.
FWIW, `sort` places "suniv" after all sun([4-9]|50)i variants.
ChenYu
> > --
> > 2.25.0
> >
On Tue, Mar 10, 2020 at 4:44 AM George Hilliard
<[email protected]> wrote:
>
> The suniv SoC has a MUSB controller like the one in A33, but with a SRAM
> region to be claimed.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
Same thing about the SoB and author.
> Signed-off-by: George Hilliard <[email protected]>
> ---
> drivers/usb/musb/sunxi.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
> index f3f76f2ac63f..76806b781844 100644
> --- a/drivers/usb/musb/sunxi.c
> +++ b/drivers/usb/musb/sunxi.c
> @@ -714,14 +714,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
> INIT_WORK(&glue->work, sunxi_musb_work);
> glue->host_nb.notifier_call = sunxi_musb_host_notifier;
>
> - if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
> + if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
> + of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
> set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
> + }
>
> if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
> set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
>
> if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
> - of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
> + of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
> + of_device_is_compatible(np, "allwinner,suniv-f1c100s-musb")) {
> set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
> set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
> }
> @@ -814,6 +817,7 @@ static int sunxi_musb_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id sunxi_musb_match[] = {
> + { .compatible = "allwinner,suniv-f1c100s-musb", },
And same thing about the ordering.
Once resolved,
Acked-by: Chen-Yu Tsai <[email protected]>
> { .compatible = "allwinner,sun4i-a10-musb", },
> { .compatible = "allwinner,sun6i-a31-musb", },
> { .compatible = "allwinner,sun8i-a33-musb", },
> --
> 2.25.0
>
Thanks for the review.
On Thu, Mar 12, 2020 at 1:51 AM Chen-Yu Tsai <[email protected]> wrote:
>
> On Tue, Mar 10, 2020 at 4:43 AM George Hilliard
> <[email protected]> wrote:
> >
> > The suniv SoC has one USB OTG port connected to a MUSB controller.
> >
> > Add support for its USB PHY.
> >
> > Signed-off-by: Icenowy Zheng <[email protected]>
>
> Not sure why Icenowy's SoB is here. If she was the original author, you
> are supposed to keep her name as the author.
So, I was unclear on the convention here. This patch is based on her
patch, but I've modified it and rebased those modifications back into
a single change. I'm happy to change the author field - does it need
a "Co-authored-by: myself" here?
> >
> > static const struct of_device_id sun4i_usb_phy_of_match[] = {
> > + { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > + .data = &suniv_f1c100s_cfg },
> > { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
>
> Please use the same style (and ignore checkpatch.pl on this one).
Very happy to change this, it was bugging me!
George
On Thu, Mar 12, 2020 at 8:06 PM George Hilliard
<[email protected]> wrote:
>
> Thanks for the review.
>
> On Thu, Mar 12, 2020 at 1:51 AM Chen-Yu Tsai <[email protected]> wrote:
> >
> > On Tue, Mar 10, 2020 at 4:43 AM George Hilliard
> > <[email protected]> wrote:
> > >
> > > The suniv SoC has one USB OTG port connected to a MUSB controller.
> > >
> > > Add support for its USB PHY.
> > >
> > > Signed-off-by: Icenowy Zheng <[email protected]>
> >
> > Not sure why Icenowy's SoB is here. If she was the original author, you
> > are supposed to keep her name as the author.
>
> So, I was unclear on the convention here. This patch is based on her
> patch, but I've modified it and rebased those modifications back into
> a single change. I'm happy to change the author field - does it need
> a "Co-authored-by: myself" here?
I suppose that really depends on how much you changed it. If it were just
stylistic changes I'd keep the original author. Also you should list any
changes you made to the patch by inserting
[<who>: changed foo and bar]
before your SoB.
As for the Co-authored-by, I haven't really seen it used so I don't really
know.
ChenYu
> > >
> > > static const struct of_device_id sun4i_usb_phy_of_match[] = {
> > > + { .compatible = "allwinner,suniv-f1c100s-usb-phy",
> > > + .data = &suniv_f1c100s_cfg },
> > > { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
> >
> > Please use the same style (and ignore checkpatch.pl on this one).
>
> Very happy to change this, it was bugging me!
>
> George
On Thu, Mar 12, 2020, 11:08 PM Chen-Yu Tsai <[email protected]> wrote:
>
> On Thu, Mar 12, 2020 at 8:06 PM George Hilliard
> <[email protected]> wrote:
> >
> > Thanks for the review.
> >
> > On Thu, Mar 12, 2020 at 1:51 AM Chen-Yu Tsai <[email protected]> wrote:
> > >
> > > On Tue, Mar 10, 2020 at 4:43 AM George Hilliard
> > > <[email protected]> wrote:
> > > >
> > > > The suniv SoC has one USB OTG port connected to a MUSB controller.
> > > >
> > > > Add support for its USB PHY.
> > > >
> > > > Signed-off-by: Icenowy Zheng <[email protected]>
> > >
> > > Not sure why Icenowy's SoB is here. If she was the original author, you
> > > are supposed to keep her name as the author.
> >
> > So, I was unclear on the convention here. This patch is based on her
> > patch, but I've modified it and rebased those modifications back into
> > a single change. I'm happy to change the author field - does it need
> > a "Co-authored-by: myself" here?
>
> I suppose that really depends on how much you changed it. If it were just
> stylistic changes I'd keep the original author. Also you should list any
> changes you made to the patch by inserting
>
> [<who>: changed foo and bar]
>
> before your SoB.
Ok, this makes sense. Thanks. I'll send another series. The few that
are stylistic, I believe I retained Icenowy as the author. Where I
modified them, I put myself (so people email me, not her, with
problems). I'll modify the commit messages like you describe and
double check the authorship.
> As for the Co-authored-by, I haven't really seen it used so I don't really
> know.
Off topic, but I wish Git supported multiple authors natively.
George