2020-03-11 13:42:24

by Eugeniy Paltsev

Subject: [PATCH 0/3] CLK: HSDK: CGU: updates for HSDK clock management

Bunch of updates for HSDK clock generation unit (CGU) driver.

Eugeniy Paltsev (3):
CLK: HSDK: CGU: check if PLL is bypassed first
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: add support for 148.5MHz clock

drivers/clk/clk-hsdk-pll.c | 70 +++++++++++++++++++++-----------------
1 file changed, 39 insertions(+), 31 deletions(-)

--
2.21.1

2020-03-11 13:48:54

by Eugeniy Paltsev

Subject: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock

Add support for 148.5MHz clock for HDMI PLL

Signed-off-by: Eugeniy Paltsev <[email protected]>
---
drivers/clk/clk-hsdk-pll.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af57a5b1..b4f8852201cb 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {

static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{ 27000000, 0, 0, 0, 0, 1 },
+ { 148500000, 0, 21, 3, 0, 0 },
{ 297000000, 0, 21, 2, 0, 0 },
{ 540000000, 0, 19, 1, 0, 0 },
{ 594000000, 0, 21, 1, 0, 0 },
--
2.21.1

2020-05-29 04:09:56

by Stephen Boyd

Subject: Re: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock

Quoting Eugeniy Paltsev (2020-03-11 06:41:15)
> Add support for 148.5MHz clock for HDMI PLL
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---

Applied to clk-next