This enables the sampling check in kernel/events/core.c's
perf_event_open, which returns the more appropriate -EOPNOTSUPP.
BEFORE:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (l3_request_g1.caching_l3_cache_accesses).
/bin/dmesg | grep -i perf may provide additional information.
With nothing relevant in dmesg.
AFTER:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
l3_request_g1.caching_l3_cache_accesses: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'
Signed-off-by: Kim Phillips <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Michael Petlan <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Fixes: c43ca5091a37 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters")
---
RESEND. No changes since original submission 19 Feb 2020:
https://lkml.org/lkml/2020/2/19/1194
arch/x86/events/amd/uncore.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index a6ea07f2aa84..4d867a752f0e 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -190,15 +190,12 @@ static int amd_uncore_event_init(struct perf_event *event)
/*
* NB and Last level cache counters (MSRs) are shared across all cores
- * that share the same NB / Last level cache. Interrupts can be directed
- * to a single target core, however, event counts generated by processes
- * running on other cores cannot be masked out. So we do not support
- * sampling and per-thread events.
+ * that share the same NB / Last level cache. On family 16h and below,
+ * Interrupts can be directed to a single target core, however, event
+ * counts generated by processes running on other cores cannot be masked
+ * out. So we do not support sampling and per-thread events via
+ * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
*/
- if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
- return -EINVAL;
-
- /* and we do not enable counter overflow interrupts */
hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
hwc->idx = -1;
@@ -306,7 +303,7 @@ static struct pmu amd_nb_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct pmu amd_llc_pmu = {
@@ -317,7 +314,7 @@ static struct pmu amd_llc_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
--
2.25.1
In order to better accommodate the upcoming Family 19h support,
given the 80-char line limit, we move the existing code into a new
l3_thread_slice_mask function, and convert it to use the more
readable topology_* helper functions.
Signed-off-by: Kim Phillips <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Michael Petlan <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
RESEND. No changes since original submission 19 Feb 2020:
https://lkml.org/lkml/2020/2/19/1192
arch/x86/events/amd/uncore.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 4d867a752f0e..e635c40ca9c4 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -180,6 +180,23 @@ static void amd_uncore_del(struct perf_event *event, int flags)
hwc->idx = -1;
}
+/*
+ * Convert logical cpu number to L3 PMC Config ThreadMask format
+ */
+static u64 l3_thread_slice_mask(int cpu)
+{
+ unsigned int shift, thread = 0;
+ u64 thread_mask, core = topology_core_id(cpu);
+
+ if (topology_smt_supported() && !topology_is_primary_thread(cpu))
+ thread = 1;
+
+ shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ thread_mask = BIT_ULL(shift);
+
+ return AMD64_L3_SLICE_MASK | thread_mask;
+}
+
static int amd_uncore_event_init(struct perf_event *event)
{
struct amd_uncore *uncore;
@@ -206,15 +223,8 @@ static int amd_uncore_event_init(struct perf_event *event)
* SliceMask and ThreadMask need to be set for certain L3 events in
* Family 17h. For other events, the two fields do not affect the count.
*/
- if (l3_mask && is_llc_event(event)) {
- int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
-
- if (smp_num_siblings > 1)
- thread += cpu_data(event->cpu).apicid & 1;
-
- hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
- AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
- }
+ if (l3_mask && is_llc_event(event))
+ hwc->config |= l3_thread_slice_mask(event->cpu);
uncore = event_to_amd_uncore(event);
if (!uncore)
--
2.25.1
Family 19h introduces a change in slice, core and thread specification
in its L3 Performance Event Select (ChL3PmcCfg) register. We implement
the new bitmask conversions in a new path in l3_thread_slice_mask()
based on a family 19h-and-above check.
We also change the uncore_init() family check to 19h-and-above, so as
to not revert to the Family 16h-or-below L2/NB code paths in the driver.
Signed-off-by: Kim Phillips <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Michael Petlan <[email protected]>
Cc: Namhyung Kim <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
RESEND. No changes since original submission:
https://lkml.org/lkml/2020/2/19/1193
arch/x86/events/amd/uncore.c | 20 ++++++++++++++------
arch/x86/include/asm/perf_event.h | 15 +++++++++++++--
2 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index e635c40ca9c4..78b4fb917ad6 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -191,10 +191,18 @@ static u64 l3_thread_slice_mask(int cpu)
if (topology_smt_supported() && !topology_is_primary_thread(cpu))
thread = 1;
- shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ if (boot_cpu_data.x86 <= 0x18) {
+ shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ thread_mask = BIT_ULL(shift);
+
+ return AMD64_L3_SLICE_MASK | thread_mask;
+ }
+
+ core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK;
+ shift = AMD64_L3_THREAD_SHIFT + thread;
thread_mask = BIT_ULL(shift);
- return AMD64_L3_SLICE_MASK | thread_mask;
+ return AMD64_L3_EN_ALL_SLICES | core | thread_mask;
}
static int amd_uncore_event_init(struct perf_event *event)
@@ -220,8 +228,8 @@ static int amd_uncore_event_init(struct perf_event *event)
return -EINVAL;
/*
- * SliceMask and ThreadMask need to be set for certain L3 events in
- * Family 17h. For other events, the two fields do not affect the count.
+ * SliceMask and ThreadMask need to be set for certain L3 events.
+ * For other events, the two fields do not affect the count.
*/
if (l3_mask && is_llc_event(event))
hwc->config |= l3_thread_slice_mask(event->cpu);
@@ -530,9 +538,9 @@ static int __init amd_uncore_init(void)
if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
return -ENODEV;
- if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+ if (boot_cpu_data.x86 >= 0x17) {
/*
- * For F17h or F18h, the Northbridge counters are
+ * For F17h and above, the Northbridge counters are
* repurposed as Data Fabric counters. Also, L3
* counters are supported too. The PMUs are exported
* based on family as either L2 or L3 and NB or DF.
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 29964b0e1075..e855e9cf2c37 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -50,11 +50,22 @@
#define AMD64_L3_SLICE_SHIFT 48
#define AMD64_L3_SLICE_MASK \
- ((0xFULL) << AMD64_L3_SLICE_SHIFT)
+ (0xFULL << AMD64_L3_SLICE_SHIFT)
+#define AMD64_L3_SLICEID_MASK \
+ (0x7ULL << AMD64_L3_SLICE_SHIFT)
#define AMD64_L3_THREAD_SHIFT 56
#define AMD64_L3_THREAD_MASK \
- ((0xFFULL) << AMD64_L3_THREAD_SHIFT)
+ (0xFFULL << AMD64_L3_THREAD_SHIFT)
+#define AMD64_L3_F19H_THREAD_MASK \
+ (0x3ULL << AMD64_L3_THREAD_SHIFT)
+
+#define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
+#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
+
+#define AMD64_L3_COREID_SHIFT 42
+#define AMD64_L3_COREID_MASK \
+ (0x7ULL << AMD64_L3_COREID_SHIFT)
#define X86_RAW_EVENT_MASK \
(ARCH_PERFMON_EVENTSEL_EVENT | \
--
2.25.1
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: f967140dfb7442e2db0868b03b961f9c59418a1b
Gitweb: https://git.kernel.org/tip/f967140dfb7442e2db0868b03b961f9c59418a1b
Author: Kim Phillips <[email protected]>
AuthorDate: Wed, 11 Mar 2020 14:13:21 -05:00
Committer: Borislav Petkov <[email protected]>
CommitterDate: Thu, 12 Mar 2020 14:08:50 +01:00
perf/amd/uncore: Replace manual sampling check with CAP_NO_INTERRUPT flag
Enable the sampling check in kernel/events/core.c::perf_event_open(),
which returns the more appropriate -EOPNOTSUPP.
BEFORE:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (l3_request_g1.caching_l3_cache_accesses).
/bin/dmesg | grep -i perf may provide additional information.
With nothing relevant in dmesg.
AFTER:
$ sudo perf record -a -e instructions,l3_request_g1.caching_l3_cache_accesses true
Error:
l3_request_g1.caching_l3_cache_accesses: PMU Hardware doesn't support sampling/overflow-interrupts. Try 'perf stat'
Fixes: c43ca5091a37 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters")
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Acked-by: Peter Zijlstra <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
---
arch/x86/events/amd/uncore.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index a6ea07f..4d867a7 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -190,15 +190,12 @@ static int amd_uncore_event_init(struct perf_event *event)
/*
* NB and Last level cache counters (MSRs) are shared across all cores
- * that share the same NB / Last level cache. Interrupts can be directed
- * to a single target core, however, event counts generated by processes
- * running on other cores cannot be masked out. So we do not support
- * sampling and per-thread events.
+ * that share the same NB / Last level cache. On family 16h and below,
+ * Interrupts can be directed to a single target core, however, event
+ * counts generated by processes running on other cores cannot be masked
+ * out. So we do not support sampling and per-thread events via
+ * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts:
*/
- if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
- return -EINVAL;
-
- /* and we do not enable counter overflow interrupts */
hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
hwc->idx = -1;
@@ -306,7 +303,7 @@ static struct pmu amd_nb_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct pmu amd_llc_pmu = {
@@ -317,7 +314,7 @@ static struct pmu amd_llc_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
};
static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
On Wed, Mar 11, 2020 at 02:13:22PM -0500, Kim Phillips wrote:
> In order to better accommodate the upcoming Family 19h support,
> given the 80-char line limit, we move the existing code into a new
> l3_thread_slice_mask function, and convert it to use the more
> readable topology_* helper functions.
>
> Signed-off-by: Kim Phillips <[email protected]>
> Cc: Alexander Shishkin <[email protected]>
> Cc: Arnaldo Carvalho de Melo <[email protected]>
> Cc: Borislav Petkov <[email protected]>
> Cc: "H. Peter Anvin" <[email protected]>
> Cc: Ingo Molnar <[email protected]>
> Cc: Ingo Molnar <[email protected]>
> Cc: Jiri Olsa <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Michael Petlan <[email protected]>
> Cc: Namhyung Kim <[email protected]>
> Cc: Peter Zijlstra <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> ---
> RESEND. No changes since original submission 19 Feb 2020:
>
> https://lkml.org/lkml/2020/2/19/1192
>
> arch/x86/events/amd/uncore.c | 28 +++++++++++++++++++---------
> 1 file changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
> index 4d867a752f0e..e635c40ca9c4 100644
> --- a/arch/x86/events/amd/uncore.c
> +++ b/arch/x86/events/amd/uncore.c
> @@ -180,6 +180,23 @@ static void amd_uncore_del(struct perf_event *event, int flags)
> hwc->idx = -1;
> }
>
> +/*
> + * Convert logical cpu number to L3 PMC Config ThreadMask format
> + */
> +static u64 l3_thread_slice_mask(int cpu)
> +{
> + unsigned int shift, thread = 0;
> + u64 thread_mask, core = topology_core_id(cpu);
> +
> + if (topology_smt_supported() && !topology_is_primary_thread(cpu))
> + thread = 1;
> +
> + shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
> + thread_mask = BIT_ULL(shift);
> +
> + return AMD64_L3_SLICE_MASK | thread_mask;
> +}
> +
> static int amd_uncore_event_init(struct perf_event *event)
> {
> struct amd_uncore *uncore;
> @@ -206,15 +223,8 @@ static int amd_uncore_event_init(struct perf_event *event)
> * SliceMask and ThreadMask need to be set for certain L3 events in
> * Family 17h. For other events, the two fields do not affect the count.
> */
> - if (l3_mask && is_llc_event(event)) {
> - int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4);
> -
> - if (smp_num_siblings > 1)
> - thread += cpu_data(event->cpu).apicid & 1;
> -
> - hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
> - AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
> - }
> + if (l3_mask && is_llc_event(event))
> + hwc->config |= l3_thread_slice_mask(event->cpu);
>
> uncore = event_to_amd_uncore(event);
> if (!uncore)
> --
If you carve out functionality into a separate function and then do
changes to that functionality, you do two patches: the first one is
doing only the mechanical move only and the second one does the changes.
Please do that with that one too.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Wed, Mar 11, 2020 at 02:13:23PM -0500, Kim Phillips wrote:
> Family 19h introduces a change in slice, core and thread specification
> in its L3 Performance Event Select (ChL3PmcCfg) register. We implement
> the new bitmask conversions in a new path in l3_thread_slice_mask()
> based on a family 19h-and-above check.
>
> We also change the uncore_init() family check to 19h-and-above, so as
> to not revert to the Family 16h-or-below L2/NB code paths in the driver.
Pls use passive voice in your commit message: no "we" or "I", etc, and
describe your changes in imperative mood.
Also, pls read section "2) Describe your changes" in
Documentation/process/submitting-patches.rst for more details.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: c43ca5091a37 ("perf/x86/amd: Add support for AMD NB and L2I "uncore" counters").
The bot has tested the following trees: v5.5.9, v5.4.25, v4.19.109, v4.14.173, v4.9.216, v4.4.216.
v5.5.9: Build OK!
v5.4.25: Build OK!
v4.19.109: Failed to apply! Possible dependencies:
88dbe3c94e27 ("perf/core, arch/x86: Strengthen exclusion checks with PERF_PMU_CAP_NO_EXCLUDE")
v4.14.173: Failed to apply! Possible dependencies:
88dbe3c94e27 ("perf/core, arch/x86: Strengthen exclusion checks with PERF_PMU_CAP_NO_EXCLUDE")
v4.9.216: Failed to apply! Possible dependencies:
1650dfd1a9bc ("x86/events, drivers/amd/iommu: Prepare for multiple IOMMUs support")
25df39f2cfd0 ("x86/events/amd/iommu: Enable support for multiple IOMMUs")
51686546304f ("x86/events/amd/iommu: Fix sysfs perf attribute groups")
6aad0c626905 ("x86/events/amd/iommu: Clean up bitwise operations")
88dbe3c94e27 ("perf/core, arch/x86: Strengthen exclusion checks with PERF_PMU_CAP_NO_EXCLUDE")
cf25f904ef75 ("x86/events/amd/iommu: Add IOMMU-specific hw_perf_event struct")
f5863a00e73c ("x86/events/amd/iommu.c: Modify functions to query max banks and counters")
f9573e53f123 ("x86/events/amd/iommu: Declare pr_fmt() format")
v4.4.216: Failed to apply! Possible dependencies:
1229735b290d ("perf/x86/intel/uncore: Make code more readable")
1a246b9f58c6 ("perf/x86/intel/uncore: Convert to hotplug state machine")
31d50c551e30 ("perf/x86/amd/uncore: Do not register a task ctx for uncore PMUs")
4f089678d071 ("perf/x86/intel/uncore: Fix error handling")
5485592c1795 ("perf/x86/intel/uncore: Make PCI and MSR uncore independent")
77af0037de0a ("perf/x86/intel/uncore: Add Knights Landing uncore PMU support")
7d762e49c211 ("perf/x86/amd/uncore: Prevent use after free")
83f8ebd2eb45 ("perf/x86/intel/uncore: Add sanity checks for PCI dev package id")
96b2bd3866a0 ("perf/x86/amd/uncore: Convert to hotplug state machine")
a46195f1782e ("perf/x86/intel/uncore: Clean up hardware on exit")
a83f4c00dd6a ("perf/x86/amd/uncore: Rename 'L2' to 'LLC'")
cf6d445f6897 ("perf/x86/uncore: Track packages, not per CPU data")
ffeda0038032 ("perf/x86/intel/uncore: Simplify error rollback")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha