The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).
But with the G12A family, the USB complex was correctly understood and
implemented correctly.
But seems the G12A architecture was derived for the GXL USB architecture,
with minor differences and looks we can share most of the USB DWC3 glue
driver.
This patchset refactors and adds callbacks to handle the architecture
difference while keeping the main code shared.
The main difference is that on GXL/GXM the USB2 PHY control registers
are mixed with the PHY registers (we already handle correctly), and
the GLUE registers are allmost (99%) the same as G12A.
But, the GXL/GXM HW is buggy, here are the quirks :
- for the DWC2 controller to reset correctly, the GLUE mux must be switched
to peripheral when the DWC2 controller probes. For now it's handled by simply
switching to device when probing the subnodes, but it may be not enough
- when manually switching from Host to Device when the USB port is not
populated (should not happen with proper Micro-USB/USB-C OTG switch), it
makes the DWC3 to crash. The only way to avoid that is to use the Host
Disconnect bit to disconnect the DWC3 controller from the port, but we can't
recover the Host functionnality unless resetting the DWC3 controller.
This bit is set when only manual switch is done, and a warning is printed
on manual switching.
The patches 1-9 should be applied first, then either waiting the next release
or if the usb maintainer can provide us a stable tag, we can use it to merge
the DT and bindings.
Changes since v1 at [1]:
- Fixed DT bindings to take in account usb2-phy2 on GXM
- Added comment in patch2
- Fixed patch 5 and moved fix out
- Collected tags
- Lower DT patch changes, switch p20x-q20x port B as OTG by default
[1] http://lkml.kernel.org/r/[email protected]
Martin Blumenstingl (4):
arm64: dts: amlogic: use the new USB control driver for GXL and GXM
phy: amlogic: meson-gxl-usb3: remove code for non-existing PHY
usb: dwc3: of-simple: remove Amlogic GXL and AXG compatibles
dt-bindings: usb: dwc3: remove old DWC3 wrapper
Neil Armstrong (10):
dt-bindings: usb: amlogic,meson-g12a-usb-ctrl: add the Amlogic GXL and
GXM Families USB Glue Bindings
usb: dwc3: meson-g12a: specify phy names in soc data
usb: dwc3: meson-g12a: handle the phy and glue registers separately
usb: dwc3: meson-g12a: get the reset as shared
usb: dwc3: meson-g12a: check return of dwc3_meson_g12a_usb_init
usb: dwc3: meson-g12a: refactor usb2 phy init
usb: dwc3: meson-g12a: refactor usb init
usb: dwc3: meson-g12a: support the GXL/GXM DWC3 host phy disconnect
usb: dwc3: meson-g12a: add support for GXL and GXM SoCs
doc: dt: bindings: usb: dwc3: remove amlogic compatible entries
.../bindings/phy/meson-gxl-usb3-phy.txt | 31 --
.../devicetree/bindings/usb/amlogic,dwc3.txt | 42 --
.../usb/amlogic,meson-g12a-usb-ctrl.yaml | 73 ++-
.../devicetree/bindings/usb/dwc3.txt | 2 -
.../dts/amlogic/meson-gx-libretech-pc.dtsi | 3 +-
.../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 3 +-
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 3 +-
.../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 +
.../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 4 +
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 +
.../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 +
.../amlogic/meson-gxl-s905x-libretech-cc.dts | 3 +-
.../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +-
.../dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 +-
.../dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-vega-s96.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 7 +-
drivers/phy/amlogic/Kconfig | 12 -
drivers/phy/amlogic/Makefile | 1 -
drivers/phy/amlogic/phy-meson-gxl-usb3.c | 283 ------------
drivers/usb/dwc3/dwc3-meson-g12a.c | 415 ++++++++++++++----
drivers/usb/dwc3/dwc3-of-simple.c | 30 +-
25 files changed, 477 insertions(+), 511 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
delete mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt
delete mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
--
2.22.0
From: Martin Blumenstingl <[email protected]>
The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).
Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-g12a-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../bindings/phy/meson-gxl-usb3-phy.txt | 31 --
drivers/phy/amlogic/Kconfig | 12 -
drivers/phy/amlogic/Makefile | 1 -
drivers/phy/amlogic/phy-meson-gxl-usb3.c | 283 ------------------
4 files changed, 327 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
delete mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
deleted file mode 100644
index 114947e1de3d..000000000000
--- a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding
-
-Required properties:
-- compatible: Should be "amlogic,meson-gxl-usb3-phy"
-- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
-- reg: The base address and length of the registers
-- interrupts: the interrupt specifier for the OTG detection
-- clocks: phandles to the clocks for
- - the USB3 PHY
- - and peripheral mode/OTG detection
-- clock-names: must contain "phy" and "peripheral"
-- resets: phandle to the reset lines for:
- - the USB3 PHY and
- - peripheral mode/OTG detection
-- reset-names: must contain "phy" and "peripheral"
-
-Optional properties:
-- phy-supply: see phy-bindings.txt in this directory
-
-
-Example:
- usb3_phy0: phy@78080 {
- compatible = "amlogic,meson-gxl-usb3-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>;
- clock-names = "phy", "peripheral";
- resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
- reset-names = "phy", "peripheral";
- };
diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
index af774ac2b934..77db9535ac6d 100644
--- a/drivers/phy/amlogic/Kconfig
+++ b/drivers/phy/amlogic/Kconfig
@@ -26,18 +26,6 @@ config PHY_MESON_GXL_USB2
GXL and GXM SoCs.
If unsure, say N.
-config PHY_MESON_GXL_USB3
- tristate "Meson GXL and GXM USB3 PHY drivers"
- default ARCH_MESON
- depends on OF && (ARCH_MESON || COMPILE_TEST)
- depends on USB_SUPPORT
- select GENERIC_PHY
- select REGMAP_MMIO
- help
- Enable this to support the Meson USB3 PHY and OTG detection
- IP block found in Meson GXL and GXM SoCs.
- If unsure, say N.
-
config PHY_MESON_G12A_USB2
tristate "Meson G12A USB2 PHY driver"
default ARCH_MESON
diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
index 11d1c42ac2be..8552e7153b99 100644
--- a/drivers/phy/amlogic/Makefile
+++ b/drivers/phy/amlogic/Makefile
@@ -2,5 +2,4 @@
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
-obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
deleted file mode 100644
index c0e9e4c16149..000000000000
--- a/drivers/phy/amlogic/phy-meson-gxl-usb3.c
+++ /dev/null
@@ -1,283 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Meson GXL USB3 PHY and OTG mode detection driver
- *
- * Copyright (C) 2018 Martin Blumenstingl <[email protected]>
- */
-
-#include <linux/bitfield.h>
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/platform_device.h>
-
-#define USB_R0 0x00
- #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
- #define USB_R0_P30_PHY_RESET BIT(6)
- #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
- #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
- #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
- #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
- #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
- #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
- #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
- #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
- #define USB_R0_U2D_ACT BIT(31)
-
-#define USB_R1 0x04
- #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
- #define USB_R1_U3H_PME_ENABLE BIT(1)
- #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
- #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
- #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
- #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
- #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
- #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
- #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
- #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
-
-#define USB_R2 0x08
- #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
- #define USB_R2_P30_CR_READ BIT(16)
- #define USB_R2_P30_CR_WRITE BIT(17)
- #define USB_R2_P30_CR_CAP_ADDR BIT(18)
- #define USB_R2_P30_CR_CAP_DATA BIT(19)
- #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
- #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
-
-#define USB_R3 0x0c
- #define USB_R3_P30_SSC_ENABLE BIT(0)
- #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
- #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
- #define USB_R3_P30_REF_SSP_EN BIT(13)
- #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
- #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
- #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
-
-#define USB_R4 0x10
- #define USB_R4_P21_PORT_RESET_0 BIT(0)
- #define USB_R4_P21_SLEEP_M0 BIT(1)
- #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
- #define USB_R4_P21_ONLY BIT(4)
-
-#define USB_R5 0x14
- #define USB_R5_ID_DIG_SYNC BIT(0)
- #define USB_R5_ID_DIG_REG BIT(1)
- #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
- #define USB_R5_ID_DIG_EN_0 BIT(4)
- #define USB_R5_ID_DIG_EN_1 BIT(5)
- #define USB_R5_ID_DIG_CURR BIT(6)
- #define USB_R5_ID_DIG_IRQ BIT(7)
- #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
- #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
-
-/* read-only register */
-#define USB_R6 0x18
- #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
- #define USB_R6_P30_CR_ACK BIT(16)
-
-struct phy_meson_gxl_usb3_priv {
- struct regmap *regmap;
- enum phy_mode mode;
- struct clk *clk_phy;
- struct clk *clk_peripheral;
- struct reset_control *reset;
-};
-
-static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = {
- .reg_bits = 8,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = USB_R6,
-};
-
-static int phy_meson_gxl_usb3_power_on(struct phy *phy)
-{
- struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
-
- regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0,
- USB_R5_ID_DIG_EN_0);
- regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1,
- USB_R5_ID_DIG_EN_1);
- regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK,
- FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
-
- return 0;
-}
-
-static int phy_meson_gxl_usb3_power_off(struct phy *phy)
-{
- struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
-
- regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, 0);
- regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, 0);
-
- return 0;
-}
-
-static int phy_meson_gxl_usb3_set_mode(struct phy *phy,
- enum phy_mode mode, int submode)
-{
- struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
-
- switch (mode) {
- case PHY_MODE_USB_HOST:
- regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, 0);
- regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0,
- 0);
- break;
-
- case PHY_MODE_USB_DEVICE:
- regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT,
- USB_R0_U2D_ACT);
- regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0,
- USB_R4_P21_SLEEP_M0);
- break;
-
- default:
- dev_err(&phy->dev, "unsupported PHY mode %d\n", mode);
- return -EINVAL;
- }
-
- priv->mode = mode;
-
- return 0;
-}
-
-static int phy_meson_gxl_usb3_init(struct phy *phy)
-{
- struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
- int ret;
-
- ret = reset_control_reset(priv->reset);
- if (ret)
- goto err;
-
- ret = clk_prepare_enable(priv->clk_phy);
- if (ret)
- goto err;
-
- ret = clk_prepare_enable(priv->clk_peripheral);
- if (ret)
- goto err_disable_clk_phy;
-
- ret = phy_meson_gxl_usb3_set_mode(phy, priv->mode, 0);
- if (ret)
- goto err_disable_clk_peripheral;
-
- regmap_update_bits(priv->regmap, USB_R1,
- USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
- FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
-
- return 0;
-
-err_disable_clk_peripheral:
- clk_disable_unprepare(priv->clk_peripheral);
-err_disable_clk_phy:
- clk_disable_unprepare(priv->clk_phy);
-err:
- return ret;
-}
-
-static int phy_meson_gxl_usb3_exit(struct phy *phy)
-{
- struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
-
- clk_disable_unprepare(priv->clk_peripheral);
- clk_disable_unprepare(priv->clk_phy);
-
- return 0;
-}
-
-static const struct phy_ops phy_meson_gxl_usb3_ops = {
- .power_on = phy_meson_gxl_usb3_power_on,
- .power_off = phy_meson_gxl_usb3_power_off,
- .set_mode = phy_meson_gxl_usb3_set_mode,
- .init = phy_meson_gxl_usb3_init,
- .exit = phy_meson_gxl_usb3_exit,
- .owner = THIS_MODULE,
-};
-
-static int phy_meson_gxl_usb3_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct phy_meson_gxl_usb3_priv *priv;
- struct resource *res;
- struct phy *phy;
- struct phy_provider *phy_provider;
- void __iomem *base;
- int ret;
-
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
- if (IS_ERR(base))
- return PTR_ERR(base);
-
- priv->regmap = devm_regmap_init_mmio(dev, base,
- &phy_meson_gxl_usb3_regmap_conf);
- if (IS_ERR(priv->regmap))
- return PTR_ERR(priv->regmap);
-
- priv->clk_phy = devm_clk_get(dev, "phy");
- if (IS_ERR(priv->clk_phy))
- return PTR_ERR(priv->clk_phy);
-
- priv->clk_peripheral = devm_clk_get(dev, "peripheral");
- if (IS_ERR(priv->clk_peripheral))
- return PTR_ERR(priv->clk_peripheral);
-
- priv->reset = devm_reset_control_array_get_shared(dev);
- if (IS_ERR(priv->reset))
- return PTR_ERR(priv->reset);
-
- /*
- * default to host mode as hardware defaults and/or boot-loader
- * behavior can result in this PHY starting up in device mode. this
- * default and the initialization in phy_meson_gxl_usb3_init ensure
- * that we reproducibly start in a known mode on all devices.
- */
- priv->mode = PHY_MODE_USB_HOST;
-
- phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops);
- if (IS_ERR(phy)) {
- ret = PTR_ERR(phy);
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to create PHY\n");
-
- return ret;
- }
-
- phy_set_drvdata(phy, priv);
-
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static const struct of_device_id phy_meson_gxl_usb3_of_match[] = {
- { .compatible = "amlogic,meson-gxl-usb3-phy", },
- { },
-};
-MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match);
-
-static struct platform_driver phy_meson_gxl_usb3_driver = {
- .probe = phy_meson_gxl_usb3_probe,
- .driver = {
- .name = "phy-meson-gxl-usb3",
- .of_match_table = phy_meson_gxl_usb3_of_match,
- },
-};
-module_platform_driver(phy_meson_gxl_usb3_driver);
-
-MODULE_AUTHOR("Martin Blumenstingl <[email protected]>");
-MODULE_DESCRIPTION("Meson GXL USB3 PHY and OTG detection driver");
-MODULE_LICENSE("GPL v2");
--
2.22.0
Signed-off-by: Neil Armstrong <[email protected]>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a47ad85..2ef0bcc30648 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -14,8 +14,6 @@ Required properties:
Exception for clocks:
clocks are optional if the parent node (i.e. glue-layer) is compatible to
one of the following:
- "amlogic,meson-axg-dwc3"
- "amlogic,meson-gxl-dwc3"
"cavium,octeon-7130-usb-uctl"
"qcom,dwc3"
"samsung,exynos5250-dwusb3"
--
2.22.0
From: Martin Blumenstingl <[email protected]>
Add the correcly architectured USB Glue node and adapt all the Amlogic
GXL and GXM board to the new organization.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../dts/amlogic/meson-gx-libretech-pc.dtsi | 3 +-
.../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 3 +-
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 3 +-
.../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 ++
.../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 4 ++
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 ++
.../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 ++
.../amlogic/meson-gxl-s905x-libretech-cc.dts | 3 +-
.../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +-
.../dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 45 ++++++++++---------
.../dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 3 +-
.../boot/dts/amlogic/meson-gxm-vega-s96.dts | 4 ++
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 7 ++-
16 files changed, 68 insertions(+), 31 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
index 248b018c83d5..ed9f89ee86a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
@@ -360,8 +360,9 @@
status = "okay";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 12d5e333e5f2..d853981f1ab5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -223,6 +223,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "otg";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
index 4d5949496596..2cfea3094f6c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
@@ -243,6 +243,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
index a1119cfb0280..867e30f1d62b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
@@ -216,6 +216,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
index b5667f1fb2c8..9ef210f17b4a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
@@ -29,3 +29,7 @@
&cvbs_vdac_port {
status = "disabled";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
index 6509c4950950..ecc9df7ca023 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts
@@ -20,3 +20,7 @@
reg = <0x0 0x0 0x0 0x40000000>;
};
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
index dd729ac2300d..6705c2082a78 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
@@ -24,3 +24,7 @@
&ir {
linux,rc-map-name = "rc-tanix-tx3mini";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 440bc23c7342..8bcdffdf55d0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -207,3 +207,7 @@
pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default";
};
+
+&usb {
+ dr_mode = "peripheral";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index e8348b2728db..e493831a80f0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -272,8 +272,9 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 62dd87821ce5..f1acca5c4434 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -218,6 +218,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 43eb7d149e36..93963e1b7fc0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -188,8 +188,9 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
&usb2_phy0 {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 259d86399390..95b301a7c725 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -14,26 +14,43 @@
compatible = "amlogic,meson-gxl";
soc {
- usb0: usb@c9000000 {
- status = "disabled";
- compatible = "amlogic,meson-gxl-dwc3";
+ usb: usb@d0078080 {
+ compatible = "amlogic,meson-gxl-usb-ctrl";
+ reg = <0x0 0xd0078080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clocks = <&clkc CLKID_USB>;
- clock-names = "usb_general";
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
- reset-names = "usb_otg";
- dwc3: dwc3@c9000000 {
+ dr_mode = "otg";
+
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+
+ dwc2: usb@c9100000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xc9100000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1>;
+ clock-names = "otg";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@c9000000 {
compatible = "snps,dwc3";
reg = <0x0 0xc9000000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
- phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
};
};
@@ -71,18 +88,6 @@
reset-names = "phy";
status = "okay";
};
-
- usb3_phy: phy@78080 {
- compatible = "amlogic,meson-gxl-usb3-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
- clock-names = "phy", "peripheral";
- resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
- reset-names = "phy", "peripheral";
- status = "okay";
- };
};
&efuse {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index f82f25c1a5f9..4310f01ccc89 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -437,6 +437,7 @@
vref-supply = <&vddio_ao18>;
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "peripheral";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index c2bd4dbbf38c..83eca3af44ce 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -179,6 +179,7 @@
pinctrl-names = "default";
};
-&usb0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
index 0bdf51d041ae..d3fdba4da9a6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
@@ -39,3 +39,7 @@
&ir {
linux,rc-map-name = "rc-vega-s9x";
};
+
+&usb {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index 5ff64a0d2dcf..84399e802188 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -141,8 +141,11 @@
compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};
-&dwc3 {
- phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
+&usb {
+ compatible = "amlogic,meson-gxm-usb-ctrl";
+
+ phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";
+ phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
};
&vdec {
--
2.22.0
Refactor the USB init code patch to handle the Amlogic GXL/GXM needing
to initialize the OTG port as Peripheral mode for the DWC2 IP to probe
correctly.
A secondary, post_init callback is added to setup the OTG PHY mode after
the sub-nodes probe.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 46 +++++++++++++++++++++---------
1 file changed, 33 insertions(+), 13 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 328e74def56f..43b398b7b1f7 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -140,6 +140,8 @@ struct dwc3_meson_g12a_drvdata {
enum phy_mode mode);
int (*set_phy_mode)(struct dwc3_meson_g12a *priv, int i,
enum phy_mode mode);
+ int (*usb_init)(struct dwc3_meson_g12a *priv);
+ int (*usb_post_init)(struct dwc3_meson_g12a *priv);
};
static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
@@ -151,6 +153,8 @@ static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
static int dwc3_meson_g12a_set_phy_mode(struct dwc3_meson_g12a *priv,
int i, enum phy_mode mode);
+static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv);
+
static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
.otg_switch_supported = true,
.clks = meson_g12a_clocks,
@@ -160,6 +164,7 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
.setup_regmaps = dwc3_meson_g12a_setup_regmaps,
.usb2_init_phy = dwc3_meson_g12a_usb2_init_phy,
.set_phy_mode = dwc3_meson_g12a_set_phy_mode,
+ .usb_init = dwc3_meson_g12a_usb_init,
};
static struct dwc3_meson_g12a_drvdata a1_drvdata = {
@@ -171,6 +176,7 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = {
.setup_regmaps = dwc3_meson_g12a_setup_regmaps,
.usb2_init_phy = dwc3_meson_g12a_usb2_init_phy,
.set_phy_mode = dwc3_meson_g12a_set_phy_mode,
+ .usb_init = dwc3_meson_g12a_usb_init,
};
struct dwc3_meson_g12a {
@@ -231,15 +237,11 @@ static int dwc3_meson_g12a_usb2_init_phy(struct dwc3_meson_g12a *priv, int i,
return 0;
}
-static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
+static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv,
+ enum phy_mode mode)
{
int i, ret;
- if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
- priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
- else
- priv->otg_phy_mode = PHY_MODE_USB_HOST;
-
for (i = 0; i < priv->drvdata->num_phys; ++i) {
if (!priv->phys[i])
continue;
@@ -284,9 +286,10 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
}
-static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
+static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv,
+ enum phy_mode mode)
{
- if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) {
+ if (mode == PHY_MODE_USB_DEVICE) {
regmap_update_bits(priv->usb_glue_regmap, USB_R0,
USB_R0_U2D_ACT, USB_R0_U2D_ACT);
regmap_update_bits(priv->usb_glue_regmap, USB_R0,
@@ -301,11 +304,12 @@ static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv)
}
}
-static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
+static int dwc3_meson_g12a_usb_init_glue(struct dwc3_meson_g12a *priv,
+ enum phy_mode mode)
{
int ret;
- ret = dwc3_meson_g12a_usb2_init(priv);
+ ret = dwc3_meson_g12a_usb2_init(priv, mode);
if (ret)
return ret;
@@ -327,7 +331,7 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
if (priv->usb3_ports)
dwc3_meson_g12a_usb3_init(priv);
- dwc3_meson_g12a_usb_otg_apply_mode(priv);
+ dwc3_meson_g12a_usb_otg_apply_mode(priv, mode);
return 0;
}
@@ -406,7 +410,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
if (ret)
return ret;
- dwc3_meson_g12a_usb_otg_apply_mode(priv);
+ dwc3_meson_g12a_usb_otg_apply_mode(priv, mode);
return 0;
}
@@ -553,6 +557,11 @@ static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv,
return 0;
}
+static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv)
+{
+ return dwc3_meson_g12a_usb_init_glue(priv, priv->otg_phy_mode);
+}
+
static int dwc3_meson_g12a_probe(struct platform_device *pdev)
{
struct dwc3_meson_g12a *priv;
@@ -620,7 +629,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
/* Get dr_mode */
priv->otg_mode = usb_get_dr_mode(dev);
- ret = dwc3_meson_g12a_usb_init(priv);
+ if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
+ priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
+ else
+ priv->otg_phy_mode = PHY_MODE_USB_HOST;
+
+ ret = priv->drvdata->usb_init(priv);
if (ret)
goto err_disable_clks;
@@ -642,6 +656,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
if (ret)
goto err_phys_power;
+ if (priv->drvdata->usb_post_init) {
+ ret = priv->drvdata->usb_post_init(priv);
+ if (ret)
+ goto err_phys_power;
+ }
+
ret = dwc3_meson_g12a_otg_init(pdev, priv);
if (ret)
goto err_phys_power;
--
2.22.0
In order to support the Amlogic GXL/GXM SoCs, the reset line must
be handled as shared since also used by the PHYs.
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 37ef08493e37..41bcbd31fe4e 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -564,7 +564,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
- priv->reset = devm_reset_control_get(dev, NULL);
+ priv->reset = devm_reset_control_get_shared(dev, NULL);
if (IS_ERR(priv->reset)) {
ret = PTR_ERR(priv->reset);
dev_err(dev, "failed to get device reset, err=%d\n", ret);
--
2.22.0
The Amlogic GXL and GXM is slightly different from the Amlogic G12A Glue.
The GXL SoCs only embeds 2 USB2 PHYs and no USB3 PHYs, and the GXM SoCs
embeds 3 USB2 PHYs.
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
.../usb/amlogic,meson-g12a-usb-ctrl.yaml | 73 ++++++++++++++++++-
1 file changed, 69 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
index b0e5e0fe9386..b0af50a7c124 100644
--- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
+++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
@@ -25,9 +25,13 @@ description: |
The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
host-only mode.
+ The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY.
+
properties:
compatible:
enum:
+ - amlogic,meson-gxl-usb-ctrl
+ - amlogic,meson-gxm-usb-ctrl
- amlogic,meson-g12a-usb-ctrl
- amlogic,meson-a1-usb-ctrl
@@ -41,6 +45,11 @@ properties:
clocks:
minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
resets:
minItems: 1
@@ -52,10 +61,8 @@ properties:
maxItems: 1
phy-names:
- items:
- - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
- - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
- - const: usb3-phy0 # USB3 PHY if USB3_0 is used
+ minItems: 1
+ maxItems: 3
phys:
minItems: 1
@@ -89,6 +96,61 @@ required:
- dr_mode
allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-g12a-usb-ctrl
+
+ then:
+ properties:
+ phy-names:
+ items:
+ - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
+ - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
+ - const: usb3-phy0 # USB3 PHY if USB3_0 is used
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-gxl-usb-ctrl
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ items:
+ - const: usb_ctrl
+ - const: ddr
+ phy-names:
+ items:
+ - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
+ - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
+ required:
+ - clock-names
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-gxm-usb-ctrl
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ items:
+ - const: usb_ctrl
+ - const: ddr
+ phy-names:
+ items:
+ - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
+ - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
+ - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used
+
+ required:
+ - clock-names
- if:
properties:
compatible:
@@ -97,6 +159,9 @@ allOf:
then:
properties:
+ phy-names:
+ items:
+ - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
clocks:
minItems: 3
clock-names:
--
2.22.0
Hi Neil,
On Thu, Mar 26, 2020 at 2:45 PM Neil Armstrong <[email protected]> wrote:
[...]
> -static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
> +static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv,
> + enum phy_mode mode)
> {
> int i, ret;
>
> - if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
> - priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
> - else
> - priv->otg_phy_mode = PHY_MODE_USB_HOST;
> -
> for (i = 0; i < priv->drvdata->num_phys; ++i) {
> if (!priv->phys[i])
> continue;
> @@ -284,9 +286,10 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
> FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
> }
There is something strange with dwc3_meson_g12a_usb2_init.
enum phy_mode mode is added here but it's not used inside this function
I also think that we should not pass enum phy_mode to
dwc3_meson_g12a_usb_otg_apply_mode
I'm aware that the original function used enum phy_mode inside but
this doesn't seem right:
we're not configuring a PHY there
instead we're setting up the OTG switch so I think we should use enum
usb_role instead
[...]
not part of this patch but should be:
there's a still a direct call to dwc3_meson_g12a_usb_init() in
dwc3_meson_g12a_resume()
I think that needs to be changed to priv->drvdata->usb_init(priv); as well
Hi,
Neil Armstrong <[email protected]> writes:
> The USB support was initialy done with a set of PHYs and dwc3-of-simple
> because the architecture of the USB complex was not understood correctly
> at the time (and proper documentation was missing...).
>
> But with the G12A family, the USB complex was correctly understood and
> implemented correctly.
> But seems the G12A architecture was derived for the GXL USB architecture,
> with minor differences and looks we can share most of the USB DWC3 glue
> driver.
>
> This patchset refactors and adds callbacks to handle the architecture
> difference while keeping the main code shared.
>
> The main difference is that on GXL/GXM the USB2 PHY control registers
> are mixed with the PHY registers (we already handle correctly), and
> the GLUE registers are allmost (99%) the same as G12A.
>
> But, the GXL/GXM HW is buggy, here are the quirks :
> - for the DWC2 controller to reset correctly, the GLUE mux must be switched
> to peripheral when the DWC2 controller probes. For now it's handled by simply
> switching to device when probing the subnodes, but it may be not enough
> - when manually switching from Host to Device when the USB port is not
> populated (should not happen with proper Micro-USB/USB-C OTG switch), it
> makes the DWC3 to crash. The only way to avoid that is to use the Host
> Disconnect bit to disconnect the DWC3 controller from the port, but we can't
> recover the Host functionnality unless resetting the DWC3 controller.
> This bit is set when only manual switch is done, and a warning is printed
> on manual switching.
>
> The patches 1-9 should be applied first, then either waiting the next release
> or if the usb maintainer can provide us a stable tag, we can use it to merge
> the DT and bindings.
>
> Changes since v1 at [1]:
> - Fixed DT bindings to take in account usb2-phy2 on GXM
> - Added comment in patch2
> - Fixed patch 5 and moved fix out
> - Collected tags
> - Lower DT patch changes, switch p20x-q20x port B as OTG by default
patches 1-6 are applied to my testing/next
--
balbi
On 29/03/2020 12:36, Felipe Balbi wrote:
>
> Hi,
>
> Neil Armstrong <[email protected]> writes:
>> The USB support was initialy done with a set of PHYs and dwc3-of-simple
>> because the architecture of the USB complex was not understood correctly
>> at the time (and proper documentation was missing...).
>>
>> But with the G12A family, the USB complex was correctly understood and
>> implemented correctly.
>> But seems the G12A architecture was derived for the GXL USB architecture,
>> with minor differences and looks we can share most of the USB DWC3 glue
>> driver.
>>
>> This patchset refactors and adds callbacks to handle the architecture
>> difference while keeping the main code shared.
>>
>> The main difference is that on GXL/GXM the USB2 PHY control registers
>> are mixed with the PHY registers (we already handle correctly), and
>> the GLUE registers are allmost (99%) the same as G12A.
>>
>> But, the GXL/GXM HW is buggy, here are the quirks :
>> - for the DWC2 controller to reset correctly, the GLUE mux must be switched
>> to peripheral when the DWC2 controller probes. For now it's handled by simply
>> switching to device when probing the subnodes, but it may be not enough
>> - when manually switching from Host to Device when the USB port is not
>> populated (should not happen with proper Micro-USB/USB-C OTG switch), it
>> makes the DWC3 to crash. The only way to avoid that is to use the Host
>> Disconnect bit to disconnect the DWC3 controller from the port, but we can't
>> recover the Host functionnality unless resetting the DWC3 controller.
>> This bit is set when only manual switch is done, and a warning is printed
>> on manual switching.
>>
>> The patches 1-9 should be applied first, then either waiting the next release
>> or if the usb maintainer can provide us a stable tag, we can use it to merge
>> the DT and bindings.
>>
>> Changes since v1 at [1]:
>> - Fixed DT bindings to take in account usb2-phy2 on GXM
>> - Added comment in patch2
>> - Fixed patch 5 and moved fix out
>> - Collected tags
>> - Lower DT patch changes, switch p20x-q20x port B as OTG by default
>
> patches 1-6 are applied to my testing/next
>
Thanks !
Neil
On 27/03/2020 00:26, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Thu, Mar 26, 2020 at 2:45 PM Neil Armstrong <[email protected]> wrote:
> [...]
>> -static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
>> +static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv,
>> + enum phy_mode mode)
>> {
>> int i, ret;
>>
>> - if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
>> - priv->otg_phy_mode = PHY_MODE_USB_DEVICE;
>> - else
>> - priv->otg_phy_mode = PHY_MODE_USB_HOST;
>> -
>> for (i = 0; i < priv->drvdata->num_phys; ++i) {
>> if (!priv->phys[i])
>> continue;
>> @@ -284,9 +286,10 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv)
>> FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127));
>> }
> There is something strange with dwc3_meson_g12a_usb2_init.
> enum phy_mode mode is added here but it's not used inside this function
You are right...
>
> I also think that we should not pass enum phy_mode to
> dwc3_meson_g12a_usb_otg_apply_mode
> I'm aware that the original function used enum phy_mode inside but
> this doesn't seem right:
> we're not configuring a PHY there
> instead we're setting up the OTG switch so I think we should use enum
> usb_role instead
Indirectly yes, we setup how the phy_mode is set in the glue, and passing
usb_role will need an useless conversion in dwc3_meson_g12a_usb_init_glue
also calling dwc3_meson_g12a_usb_otg_apply_mode.
>
> [...]
> not part of this patch but should be:
> there's a still a direct call to dwc3_meson_g12a_usb_init() in
> dwc3_meson_g12a_resume()
> I think that needs to be changed to priv->drvdata->usb_init(priv); as well
>
Indeed, I'll fix that.
Again, thanks for reviewing !
Neil
On Thu, 26 Mar 2020 14:44:53 +0100, Neil Armstrong wrote:
> The Amlogic GXL and GXM is slightly different from the Amlogic G12A Glue.
>
> The GXL SoCs only embeds 2 USB2 PHYs and no USB3 PHYs, and the GXM SoCs
> embeds 3 USB2 PHYs.
>
> Reviewed-by: Martin Blumenstingl <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> .../usb/amlogic,meson-g12a-usb-ctrl.yaml | 73 ++++++++++++++++++-
> 1 file changed, 69 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Thu, 26 Mar 2020 14:45:05 +0100, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 2 --
> 1 file changed, 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
Neil Armstrong <[email protected]> writes:
> From: Martin Blumenstingl <[email protected]>
>
> Add the correcly architectured USB Glue node and adapt all the Amlogic
> GXL and GXM board to the new organization.
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
Queued for v5.8,
Kevin