This is the first batch of fixes and updates for the Meson8/8b/8m2
clock controller driver.
The first patch fixes the video clock hierarchy. Special thanks to
Neil for providing a lot of details about the video clock tree!
The second and third came up while testing video output on my EC-100
(Endless Mini). This board is special because u-boot does not enable
the video outputs like most other u-boot versions do. However, this
is very useful for development because it shows (the hard way ;))
where the existing code is buggy.
The last patch is a small improvement for the VPU clock so we
utilize the glitch-free mux (on SoCs which support it) and avoid
problems by changing the "live" clock tree at runtime (with the mali
clock this resulted in system hangs/freezes).
In my opinion all of these patches - including the fixes - can go to
"next" because the relevant clock trees are still read-only.
Martin Blumenstingl (4):
clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
clk: meson: meson8b: Fix the polarity of the RESET_N lines
clk: meson: meson8b: Fix the vclk_div{1,2,4,6,12}_en gate bits
clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
drivers/clk/meson/meson8b.c | 107 +++++++++++++++++++++++++-----------
1 file changed, 75 insertions(+), 32 deletions(-)
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2.26.0