2020-04-20 13:05:15

by Clément Péron

[permalink] [raw]
Subject: [PATCH v5 0/9] Add support for Allwinner H6 DVFS

Hi,

This is the same as v4 and v3 on top.
I have also fix the commit title for Pine H64 as we now only enable CPU DVFS.

Sorry for the noise,
Clément

Clément Péron (6):
arm64: configs: Enable sun50i cpufreq nvmem
arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: Sort Pine H64 device-tree nodes
arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64

Ondrej Jirman (2):
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Yangtao Li (1):
arm64: dts: allwinner: h6: Add clock to CPU cores

.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 +-
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 43 ++++---
.../dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 ++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 36 ++++++
arch/arm64/configs/defconfig | 1 +
7 files changed, 207 insertions(+), 19 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

--
2.20.1


2020-04-20 13:05:16

by Clément Péron

[permalink] [raw]
Subject: [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map

From: Ondrej Jirman <[email protected]>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 370e77b86fe1..60da1627772b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -964,6 +964,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};

gpu-thermal {
--
2.20.1

2020-04-20 13:06:47

by Clément Péron

[permalink] [raw]
Subject: [PATCH v5 7/9] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6

Enable CPU opp tables for Tanix TX6.

Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.

This voltage has been found using a voltmeter and could be wrong.

Signed-off-by: Clément Péron <[email protected]>
---
.../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
index 83e6cb0e59ce..be81330db14f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -37,6 +38,17 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_vdd_cpu_gpu: vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu_gpu>;
};

&de {
@@ -56,6 +68,7 @@
};

&gpu {
+ mali-supply = <&reg_vdd_cpu_gpu>;
status = "okay";
};

--
2.20.1

2020-04-20 13:06:49

by Clément Péron

[permalink] [raw]
Subject: [PATCH v5 8/9] arm64: dts: allwinner: Sort Pine H64 device-tree nodes

Pine H64 device-tree have some nodes not properly sorted.

Fix this.

Signed-off-by: Clément Péron <[email protected]>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b0642d841933..63a785b534e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -80,6 +80,18 @@
};
};

+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
&emac {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -91,17 +103,6 @@
status = "okay";
};

-&mdio {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-&de {
- status = "okay";
-};
-
&gpu {
mali-supply = <&reg_dcdcc>;
status = "okay";
@@ -117,12 +118,11 @@
};
};

-&ehci0 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};

&mmc0 {
--
2.20.1

2020-04-20 13:07:10

by Clément Péron

[permalink] [raw]
Subject: [PATCH v5 3/9] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

From: Ondrej Jirman <[email protected]>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
---
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..9ebd97b04b1a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <[email protected]>
+// Copyright (C) 2020 Clément Péron <[email protected]>
+
+/ {
+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp@480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1608000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {
+ reg = <0x1c 0x4>;
+ };
};

watchdog: watchdog@30090a0 {
--
2.20.1

2020-04-20 16:37:13

by Maxime Ripard

[permalink] [raw]
Subject: Re: [PATCH v5 0/9] Add support for Allwinner H6 DVFS

On Mon, Apr 20, 2020 at 03:00:12PM +0200, Cl?ment P?ron wrote:
> Hi,
>
> This is the same as v4 and v3 on top.
> I have also fix the commit title for Pine H64 as we now only enable CPU DVFS.
>
> Sorry for the noise,
> Cl?ment

I dropped the previous ones and applied, thanks!
Maxime

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2020-04-20 16:38:18

by Ondřej Jirman

[permalink] [raw]
Subject: Re: [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map

Hi,

On Mon, Apr 20, 2020 at 03:00:14PM +0200, Cl?ment P?ron wrote:
> From: Ondrej Jirman <[email protected]>
>
> This enables passive cooling by down-regulating CPU voltage
> and frequency.

Does this not produce a lot of warnings for you during compilation?

regards,
o.

> Signed-off-by: Ondrej Jirman <[email protected]>
> Signed-off-by: Cl?ment P?ron <[email protected]>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 370e77b86fe1..60da1627772b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -964,6 +964,30 @@
> polling-delay-passive = <0>;
> polling-delay = <0>;
> thermal-sensors = <&ths 0>;
> +
> + trips {
> + cpu_alert: cpu-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu-crit {
> + temperature = <100000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> };
>
> gpu-thermal {
> --
> 2.20.1
>

2020-04-20 16:41:39

by Clément Péron

[permalink] [raw]
Subject: Re: [PATCH v5 2/9] arm64: dts: allwinner: h6: Add thermal trip points/cooling map

Hi Ondrej,

On Mon, 20 Apr 2020 at 15:46, Ondřej Jirman <[email protected]> wrote:
>
> Hi,
>
> On Mon, Apr 20, 2020 at 03:00:14PM +0200, Clément Péron wrote:
> > From: Ondrej Jirman <[email protected]>
> >
> > This enables passive cooling by down-regulating CPU voltage
> > and frequency.
>
> Does this not produce a lot of warnings for you during compilation?

I got flooded by lots of warnings, from sun50i-a64, stringray-usb,
ipq6018 and didn't see but two are from sun50i-h6.

The #cooling-cells property is missing for CPU.

Will send a patch for noticing.

Regard,
Clement



>
> regards,
> o.
>
> > Signed-off-by: Ondrej Jirman <[email protected]>
> > Signed-off-by: Clément Péron <[email protected]>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 370e77b86fe1..60da1627772b 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -964,6 +964,30 @@
> > polling-delay-passive = <0>;
> > polling-delay = <0>;
> > thermal-sensors = <&ths 0>;
> > +
> > + trips {
> > + cpu_alert: cpu-alert {
> > + temperature = <85000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + cpu-crit {
> > + temperature = <100000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert>;
> > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > };
> >
> > gpu-thermal {
> > --
> > 2.20.1
> >