After guarding SOFT_DIRTY with config option, it won't occupy
precious page table bit on systems that didn't enable SOFT_DIRTY.
It can prevent page btis overflow on MIPS32R2 systems with RIXI
enabled.
Signed-off-by: Jiaxun Yang <[email protected]>
Reported-by: Thomas Bogendoerfer <[email protected]>
---
arch/mips/include/asm/pgtable-bits.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index d43fb6f8af14..e26dc41a8a68 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -55,7 +55,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
+#endif
};
/*
@@ -85,7 +87,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
+#endif
};
#elif defined(CONFIG_CPU_R3K_TLB)
@@ -101,7 +105,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo) */
_PAGE_GLOBAL_SHIFT = 8,
@@ -128,7 +134,9 @@ enum pgtable_bits {
#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
_PAGE_SPECIAL_SHIFT,
#endif
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
_PAGE_SOFT_DIRTY_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_CPU_HAS_RIXI)
_PAGE_NO_EXEC_SHIFT,
@@ -155,7 +163,11 @@ enum pgtable_bits {
#else
# define _PAGE_SPECIAL 0
#endif
-#define _PAGE_SOFT_DIRTY (1 << _PAGE_SOFT_DIRTY_SHIFT)
+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
+# define _PAGE_SOFT_DIRTY (1 << _PAGE_SOFT_DIRTY_SHIFT)
+#else
+# define _PAGE_SOFT_DIRTY 0
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_XPA)
--
2.26.0.rc2
64bit systems always have enough page table bits.
So we can safely enable it for all of them instead of for Loongson
only.
If oneday 32bit systems get 64bit PTEs than we can drop this
limition.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 85011023839b..743ed9b9099e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -45,6 +45,7 @@ config MIPS
select HAVE_ARCH_MMAP_RND_BITS if MMU
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
select HAVE_ARCH_SECCOMP_FILTER
+ select HAVE_ARCH_SOFT_DIRTY if 64BIT
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
select HAVE_ASM_MODVERSIONS
@@ -495,7 +496,6 @@ config MACH_LOONGSON64
select COMMON_CLK
select USE_OF
select BUILTIN_DTB
- select HAVE_ARCH_SOFT_DIRTY
help
This enables the support of Loongson-2/3 family of machines.
--
2.26.0.rc2
Hello!
On 26.04.2020 20:40, Jiaxun Yang wrote:
> 64bit systems always have enough page table bits.
> So we can safely enable it for all of them instead of for Loongson
> only.
>
> If oneday 32bit systems get 64bit PTEs than we can drop this
> limition.
Limitation?
> Signed-off-by: Jiaxun Yang <[email protected]>
[...]
MBR, Sergei