The LS7A bridge chip has been released for several years since the
second half of 2017, but it is not supported by the Linux mainline
kernel while it only works well with the Loongson internal kernel
version. When I update the latest version of Linux mainline kernel
on the Loongson 3A3000 CPU and LS7A bridge chip system, the boot
process failed and I feel depressed.
The LS7A bridge chip is used a lot with 3A3000 or 3A4000 CPU in
the most Loongson desktop and sever products, it is important to
support LS7A bridge chip by the Linux mainline kernel.
This patch series adds the basic support for the LS7A bridge chip,
the patch about vendor ID and SATA has been merged into the mainline
tree, the next work is to refactor the code about the interrupt
controller, and then power management and some other controller
device drivers.
By the way, if you want the boot process is successful (just for
test) on the Loongson 3A3000 CPU and LS7A bridge chip system,
you should not only apply these patches, but also need the support
for SATA and interrupt controller in the v1 patch series.
This patch series is based on mips-next.
If you have any questions and suggestions, please let me know.
Thanks,
Tiezhu Yang
v2:
- The split patch series about Loongson vendor ID and SATA controller
has been merged into the linux-block.git by Jens Axboe [1].
- Think about using hierarchy IRQ domain in the patch of interrupt
controller, and this maybe depend on the patch series by Jiaxun
("Modernize Loongson64 Machine"), so the patch about interrupt is
not included in this v2 patch series.
v3:
- The split patch series about Loongson vendor ID and SATA controller
has been merged into the mainline tree [2]
- Modify the macro definition and add comment to make it easy to read
- Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
- Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
v4:
- Use LS7A instead of Loongson 7A1000 in the description
- Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
[1] https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=9acb9fe18d86
https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=e49bd683e00b
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e49bd683e00b
Tiezhu Yang (3):
MIPS: Loongson: Get host bridge information
MIPS: Loongson: Add DMA support for LS7A
MIPS: Loongson: Add PCI support for LS7A
arch/mips/include/asm/mach-loongson64/boot_param.h | 20 +++++++
arch/mips/loongson64/dma.c | 9 ++--
arch/mips/loongson64/env.c | 22 ++++++++
arch/mips/loongson64/init.c | 17 ++++++
arch/mips/pci/fixup-loongson3.c | 12 +++++
arch/mips/pci/ops-loongson3.c | 63 ++++++++++++++++++++--
6 files changed, 136 insertions(+), 7 deletions(-)
--
2.1.0
Add PCI support for LS7A to detect PCI device.
Signed-off-by: Tiezhu Yang <[email protected]>
---
v3:
- Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
- Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
PCI_VENDOR_ID_LOONGSON depends on the mainline tree's commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
v4:
- Use LS7A instead of Loongson 7A1000 in the description
- Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
arch/mips/include/asm/mach-loongson64/boot_param.h | 9 ++++
arch/mips/loongson64/env.c | 2 +
arch/mips/pci/fixup-loongson3.c | 12 +++++
arch/mips/pci/ops-loongson3.c | 63 ++++++++++++++++++++--
4 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 4ac7034..02dcdf2 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -197,6 +197,7 @@ enum loongson_bridge_type {
LS7A = 2
};
+struct pci_bus;
struct loongson_system_configuration {
u32 nr_cpus;
u32 nr_nodes;
@@ -222,6 +223,8 @@ struct loongson_system_configuration {
struct sensor_device sensors[MAX_SENSORS];
u64 workarounds;
void (*early_config)(void);
+ int (*pci_config_access)(unsigned char access_type, struct pci_bus *bus,
+ unsigned int devfn, int where, u32 *data);
};
extern struct efi_memory_map_loongson *loongson_memmap;
@@ -230,5 +233,11 @@ extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset;
extern void rs780e_early_config(void);
extern void ls7a_early_config(void);
+extern int rs780e_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data);
+extern int ls7a_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data);
#endif
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index d11bc34..9b206ed 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -193,9 +193,11 @@ void __init prom_init_env(void)
pr_info("The bridge chip is LS7A\n");
loongson_sysconf.bridgetype = LS7A;
loongson_sysconf.early_config = ls7a_early_config;
+ loongson_sysconf.pci_config_access = ls7a_pci_config_access;
} else {
pr_info("The bridge chip is RS780E or SR5690\n");
loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config;
+ loongson_sysconf.pci_config_access = rs780e_pci_config_access;
}
}
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
index 8a741c2..6e7514c 100644
--- a/arch/mips/pci/fixup-loongson3.c
+++ b/arch/mips/pci/fixup-loongson3.c
@@ -64,6 +64,18 @@ static void pci_fixup_radeon(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
+static void ls7a_pci_class_quirk(struct pci_dev *dev)
+{
+ dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a09,
+ ls7a_pci_class_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a19,
+ ls7a_pci_class_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a29,
+ ls7a_pci_class_quirk);
+
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
index 2f6ad36..fba55dd 100644
--- a/arch/mips/pci/ops-loongson3.c
+++ b/arch/mips/pci/ops-loongson3.c
@@ -13,7 +13,10 @@
#define HT1LO_PCICFG_BASE 0x1a000000
#define HT1LO_PCICFG_BASE_TP1 0x1b000000
-static int loongson3_pci_config_access(unsigned char access_type,
+#define HT1LO_PCICFG_BASE_EXT 0xefe00000000
+#define HT1LO_PCICFG_BASE_TP1_EXT 0xefe10000000
+
+int rs780e_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn,
int where, u32 *data)
{
@@ -62,11 +65,63 @@ static int loongson3_pci_config_access(unsigned char access_type,
return PCIBIOS_SUCCESSFUL;
}
+
+int ls7a_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data)
+{
+ u_int64_t addr;
+ void *addrp;
+ unsigned char busnum = bus->number;
+ int device = PCI_SLOT(devfn);
+ int function = PCI_FUNC(devfn);
+ int reg = where & ~3;
+
+ if (where >= PCI_CFG_SPACE_EXP_SIZE)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (busnum == 0 && device > 23)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
+ addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+ if (busnum == 0) {
+ addr = HT1LO_PCICFG_BASE | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ } else {
+ addr = HT1LO_PCICFG_BASE_TP1 | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ }
+ } else { /* extended config */
+ reg = (reg & 0xff) | ((reg & 0xf00) << 16);
+ addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+ if (busnum == 0) {
+ addr = HT1LO_PCICFG_BASE_EXT | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ } else {
+ addr = HT1LO_PCICFG_BASE_TP1_EXT | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ }
+ }
+
+ if (access_type == PCI_ACCESS_WRITE)
+ *(unsigned int *)addrp = cpu_to_le32(*data);
+ else {
+ *data = le32_to_cpu(*(unsigned int *)addrp);
+ if (*data == 0xffffffff) {
+ *data = -1;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
u32 data = 0;
- int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+ int ret = loongson_sysconf.pci_config_access(PCI_ACCESS_READ,
bus, devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
@@ -91,7 +146,7 @@ static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
if (size == 4)
data = val;
else {
- ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+ ret = loongson_sysconf.pci_config_access(PCI_ACCESS_READ,
bus, devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
@@ -104,7 +159,7 @@ static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
(val << ((where & 3) << 3));
}
- ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
+ ret = loongson_sysconf.pci_config_access(PCI_ACCESS_WRITE,
bus, devfn, where, &data);
return ret;
--
2.1.0
Read the address of host bridge configuration space to get the vendor ID
and device ID of host bridge, and then we can distinguish various types
of host bridge such as LS7A or RS780E.
Signed-off-by: Tiezhu Yang <[email protected]>
---
v3:
- Modify the macro definition HOST_BRIDGE_CONFIG_ADDR and
add comment to make it easy to read.
- Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
PCI_VENDOR_ID_LOONGSON depends on the mainline tree's commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
v4:
- Use LS7A instead of Loongson 7A1000 in the description
- Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
arch/mips/include/asm/mach-loongson64/boot_param.h | 6 ++++++
arch/mips/loongson64/env.c | 18 ++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 2ed483e..fc9f14b 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -192,6 +192,11 @@ struct boot_params {
struct efi_reset_system_t reset_system;
};
+enum loongson_bridge_type {
+ RS780E = 1,
+ LS7A = 2
+};
+
struct loongson_system_configuration {
u32 nr_cpus;
u32 nr_nodes;
@@ -200,6 +205,7 @@ struct loongson_system_configuration {
u16 boot_cpu_id;
u16 reserved_cpus_mask;
enum loongson_cpu_type cputype;
+ enum loongson_bridge_type bridgetype;
u64 ht_control_base;
u64 pci_mem_start_addr;
u64 pci_mem_end_addr;
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 2554ef1..71f4aaf 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -14,12 +14,15 @@
* Author: Wu Zhangjin, [email protected]
*/
#include <linux/export.h>
+#include <linux/pci_ids.h>
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
#include <builtin_dtbs.h>
#include <workarounds.h>
+#define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
+
u32 cpu_clock_freq;
EXPORT_SYMBOL(cpu_clock_freq);
struct efi_memory_map_loongson *loongson_memmap;
@@ -43,6 +46,8 @@ void __init prom_init_env(void)
struct system_loongson *esys;
struct efi_cpuinfo_loongson *ecpu;
struct irq_source_routing_table *eirq_source;
+ u32 id;
+ u16 vendor, device;
/* firmware arguments are initialized in head.S */
boot_p = (struct boot_params *)fw_arg2;
@@ -178,4 +183,17 @@ void __init prom_init_env(void)
memcpy(loongson_sysconf.sensors, esys->sensors,
sizeof(struct sensor_device) * loongson_sysconf.nr_sensors);
pr_info("CpuClock = %u\n", cpu_clock_freq);
+
+ /* Read the ID of PCI host bridge to detect bridge type */
+ id = readl(HOST_BRIDGE_CONFIG_ADDR);
+ vendor = id & 0xffff;
+ device = (id >> 16) & 0xffff;
+
+ if (vendor == PCI_VENDOR_ID_LOONGSON && device == 0x7a00) {
+ pr_info("The bridge chip is LS7A\n");
+ loongson_sysconf.bridgetype = LS7A;
+ } else {
+ pr_info("The bridge chip is RS780E or SR5690\n");
+ loongson_sysconf.bridgetype = RS780E;
+ }
}
--
2.1.0
In the current market, the most used bridge chip on the Loongson platform
are RS780E and LS7A, the RS780E bridge chip is already supported by the
mainline kernel.
If use the default implementation of __phys_to_dma() and __dma_to_phys()
in dma-direct.h when CONFIG_ARCH_HAS_PHYS_TO_DMA is not set, it works
well used with LS7A on the Loongson single-way and multi-way platform,
and also works well used with RS780E on the Loongson single-way platform,
but the DMA address will be wrong on the non-node0 used with RS780E on
the Loongson multi-way platform.
Just as the description in the code comment, the devices get node id from
40 bit of HyperTransport bus, so we extract 2 bit node id (bit 44~45) from
48 bit address space of Loongson CPU and embed it into HyperTransport bus
(bit 37-38), this operation can be done only at the software level used
with RS780E on the Loongson multi-way platform, because it has no hardware
function to translate address of node id, this is a hardware compatibility
problem.
Device
|
| DMA address
|
Host Bridge
|
| HT bus address (40 bit)
|
CPU
|
| physical address (48 bit)
|
RAM
The LS7A has dma_node_id_offset field in the DMA route config register,
the hardware can use the dma_node_id_offset to translate address of
node id automatically, so we can get correct address when just use the
dma_pfn_offset field in struct device.
For the above reasons, in order to maintain downward compatibility
to support the RS780E bridge chip, it is better to use the platform
dependent implementation of __phys_to_dma() and __dma_to_phys().
Signed-off-by: Tiezhu Yang <[email protected]>
---
v3:
- Modify the macro definition NODE_ID_OFFSET_ADDR to
make it easy to read
- update the commit message
v4:
- Use LS7A instead of Loongson 7A1000 in the description
- Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
arch/mips/include/asm/mach-loongson64/boot_param.h | 5 +++++
arch/mips/loongson64/dma.c | 9 ++++++---
arch/mips/loongson64/env.c | 2 ++
arch/mips/loongson64/init.c | 17 +++++++++++++++++
4 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index fc9f14b..4ac7034 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -221,9 +221,14 @@ struct loongson_system_configuration {
u32 nr_sensors;
struct sensor_device sensors[MAX_SENSORS];
u64 workarounds;
+ void (*early_config)(void);
};
extern struct efi_memory_map_loongson *loongson_memmap;
extern struct loongson_system_configuration loongson_sysconf;
+extern u32 node_id_offset;
+extern void rs780e_early_config(void);
+extern void ls7a_early_config(void);
+
#endif
diff --git a/arch/mips/loongson64/dma.c b/arch/mips/loongson64/dma.c
index 5e86635..dbfe6e8 100644
--- a/arch/mips/loongson64/dma.c
+++ b/arch/mips/loongson64/dma.c
@@ -2,21 +2,24 @@
#include <linux/dma-direct.h>
#include <linux/init.h>
#include <linux/swiotlb.h>
+#include <boot_param.h>
dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
* Loongson-3's 48bit address space and embed it into 40bit */
long nid = (paddr >> 44) & 0x3;
- return ((nid << 44) ^ paddr) | (nid << 37);
+
+ return ((nid << 44) ^ paddr) | (nid << node_id_offset);
}
phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
/* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from
* Loongson-3's 48bit address space and embed it into 40bit */
- long nid = (daddr >> 37) & 0x3;
- return ((nid << 37) ^ daddr) | (nid << 44);
+ long nid = (daddr >> node_id_offset) & 0x3;
+
+ return ((nid << node_id_offset) ^ daddr) | (nid << 44);
}
void __init plat_swiotlb_setup(void)
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index 71f4aaf..d11bc34 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -192,8 +192,10 @@ void __init prom_init_env(void)
if (vendor == PCI_VENDOR_ID_LOONGSON && device == 0x7a00) {
pr_info("The bridge chip is LS7A\n");
loongson_sysconf.bridgetype = LS7A;
+ loongson_sysconf.early_config = ls7a_early_config;
} else {
pr_info("The bridge chip is RS780E or SR5690\n");
loongson_sysconf.bridgetype = RS780E;
+ loongson_sysconf.early_config = rs780e_early_config;
}
}
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index da38944..06625d6 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -13,6 +13,11 @@
#include <asm/fw/fw.h>
#include <loongson.h>
+#include <boot_param.h>
+
+#define NODE_ID_OFFSET_ADDR ((void __iomem *)TO_UNCAC(0x1001041c))
+
+u32 node_id_offset;
static void __init mips_nmi_setup(void)
{
@@ -24,6 +29,16 @@ static void __init mips_nmi_setup(void)
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}
+void rs780e_early_config(void)
+{
+ node_id_offset = 37;
+}
+
+void ls7a_early_config(void)
+{
+ node_id_offset = ((readl(NODE_ID_OFFSET_ADDR) >> 8) & 0x1f) + 36;
+}
+
void __init prom_init(void)
{
fw_init_cmdline();
@@ -33,6 +48,8 @@ void __init prom_init(void)
set_io_port_base((unsigned long)
ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
+ loongson_sysconf.early_config();
+
prom_init_numa_memory();
/* Hardcode to CPU UART 0 */
--
2.1.0
On 04/03/2020 05:29 PM, Tiezhu Yang wrote:
> The LS7A bridge chip has been released for several years since the
> second half of 2017, but it is not supported by the Linux mainline
> kernel while it only works well with the Loongson internal kernel
> version. When I update the latest version of Linux mainline kernel
> on the Loongson 3A3000 CPU and LS7A bridge chip system, the boot
> process failed and I feel depressed.
>
> The LS7A bridge chip is used a lot with 3A3000 or 3A4000 CPU in
> the most Loongson desktop and sever products, it is important to
> support LS7A bridge chip by the Linux mainline kernel.
>
> This patch series adds the basic support for the LS7A bridge chip,
> the patch about vendor ID and SATA has been merged into the mainline
> tree, the next work is to refactor the code about the interrupt
> controller, and then power management and some other controller
> device drivers.
>
> By the way, if you want the boot process is successful (just for
> test) on the Loongson 3A3000 CPU and LS7A bridge chip system,
> you should not only apply these patches, but also need the support
> for SATA and interrupt controller in the v1 patch series.
>
> This patch series is based on mips-next.
>
> If you have any questions and suggestions, please let me know.
>
> Thanks,
>
> Tiezhu Yang
>
> v2:
> - The split patch series about Loongson vendor ID and SATA controller
> has been merged into the linux-block.git by Jens Axboe [1].
>
> - Think about using hierarchy IRQ domain in the patch of interrupt
> controller, and this maybe depend on the patch series by Jiaxun
> ("Modernize Loongson64 Machine"), so the patch about interrupt is
> not included in this v2 patch series.
>
> v3:
> - The split patch series about Loongson vendor ID and SATA controller
> has been merged into the mainline tree [2]
>
> - Modify the macro definition and add comment to make it easy to read
>
> - Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
>
> - Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
>
> v4:
> - Use LS7A instead of Loongson 7A1000 in the description
> - Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=9acb9fe18d86
> https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=e49bd683e00b
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e49bd683e00b
>
> Tiezhu Yang (3):
> MIPS: Loongson: Get host bridge information
> MIPS: Loongson: Add DMA support for LS7A
> MIPS: Loongson: Add PCI support for LS7A
>
> arch/mips/include/asm/mach-loongson64/boot_param.h | 20 +++++++
> arch/mips/loongson64/dma.c | 9 ++--
> arch/mips/loongson64/env.c | 22 ++++++++
> arch/mips/loongson64/init.c | 17 ++++++
> arch/mips/pci/fixup-loongson3.c | 12 +++++
> arch/mips/pci/ops-loongson3.c | 63 ++++++++++++++++++++--
> 6 files changed, 136 insertions(+), 7 deletions(-)
>
Hi Thomas,
Could you please apply the following two patches to mips-next?
[v4,1/3] MIPS: Loongson: Get host bridge information
https://lore.kernel.org/patchwork/patch/1220009/
[v4,2/3] MIPS: Loongson: Add DMA support for LS7A
https://lore.kernel.org/patchwork/patch/1220010/
Thanks,
Tiezhu Yang
On Mon, 27 Apr 2020 09:31:54 +0800
Tiezhu Yang <[email protected]> wrote:
> On 04/03/2020 05:29 PM, Tiezhu Yang wrote:
> > The LS7A bridge chip has been released for several years since the
> > second half of 2017, but it is not supported by the Linux mainline
> > kernel while it only works well with the Loongson internal kernel
> > version. When I update the latest version of Linux mainline kernel
> > on the Loongson 3A3000 CPU and LS7A bridge chip system, the boot
> > process failed and I feel depressed.
> >
> > The LS7A bridge chip is used a lot with 3A3000 or 3A4000 CPU in
> > the most Loongson desktop and sever products, it is important to
> > support LS7A bridge chip by the Linux mainline kernel.
> >
> > This patch series adds the basic support for the LS7A bridge chip,
> > the patch about vendor ID and SATA has been merged into the mainline
> > tree, the next work is to refactor the code about the interrupt
> > controller, and then power management and some other controller
> > device drivers.
> >
> > By the way, if you want the boot process is successful (just for
> > test) on the Loongson 3A3000 CPU and LS7A bridge chip system,
> > you should not only apply these patches, but also need the support
> > for SATA and interrupt controller in the v1 patch series.
> >
> > This patch series is based on mips-next.
> >
> > If you have any questions and suggestions, please let me know.
> >
> > Thanks,
> >
> > Tiezhu Yang
> >
> > v2:
> > - The split patch series about Loongson vendor ID and SATA
> > controller has been merged into the linux-block.git by Jens Axboe
> > [1].
> >
> > - Think about using hierarchy IRQ domain in the patch of
> > interrupt controller, and this maybe depend on the patch series by
> > Jiaxun ("Modernize Loongson64 Machine"), so the patch about
> > interrupt is not included in this v2 patch series.
> >
> > v3:
> > - The split patch series about Loongson vendor ID and SATA
> > controller has been merged into the mainline tree [2]
> >
> > - Modify the macro definition and add comment to make it easy to
> > read
> >
> > - Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
> >
> > - Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
> >
> > v4:
> > - Use LS7A instead of Loongson 7A1000 in the description
> > - Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=9acb9fe18d86
> > https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=e49bd683e00b
> > [2]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e49bd683e00b
> >
> > Tiezhu Yang (3):
> > MIPS: Loongson: Get host bridge information
> > MIPS: Loongson: Add DMA support for LS7A
> > MIPS: Loongson: Add PCI support for LS7A
> >
> > arch/mips/include/asm/mach-loongson64/boot_param.h | 20 +++++++
> > arch/mips/loongson64/dma.c | 9 ++--
> > arch/mips/loongson64/env.c | 22 ++++++++
> > arch/mips/loongson64/init.c | 17 ++++++
> > arch/mips/pci/fixup-loongson3.c | 12 +++++
> > arch/mips/pci/ops-loongson3.c | 63
> > ++++++++++++++++++++-- 6 files changed, 136 insertions(+), 7
> > deletions(-)
>
> Hi Thomas,
>
> Could you please apply the following two patches to mips-next?
>
> [v4,1/3] MIPS: Loongson: Get host bridge information
> https://lore.kernel.org/patchwork/patch/1220009/
>
> [v4,2/3] MIPS: Loongson: Add DMA support for LS7A
> https://lore.kernel.org/patchwork/patch/1220010/
Sorry but I really don't like the DMA patch, hard coding a config
register in platform code is not necessarily a good idea, it
create painful hell for adding new platform support.
I'm trying very hard to let all devices go through DeviceTree.
I'd suggest you to limit DMA capability on LS7A PCH instead of doing
the hack.
Or if you think the function is necessary, you can create a DeviceTree
node called "loongson,ls7a-syscon", and do whatever you like in
init_calls by parsing this node.
Also that will also block my upcoming LS2K support patches.
You can check my tree here[1].
Thanks.
[1]: https://github.com/FlyGoat/linux/commits/next-testing-2k
>
> Thanks,
> Tiezhu Yang
>
--
Jiaxun Yang
On 04/27/2020 12:57 PM, Jiaxun Yang wrote:
> On Mon, 27 Apr 2020 09:31:54 +0800
> Tiezhu Yang <[email protected]> wrote:
>
>> On 04/03/2020 05:29 PM, Tiezhu Yang wrote:
>>> The LS7A bridge chip has been released for several years since the
>>> second half of 2017, but it is not supported by the Linux mainline
>>> kernel while it only works well with the Loongson internal kernel
>>> version. When I update the latest version of Linux mainline kernel
>>> on the Loongson 3A3000 CPU and LS7A bridge chip system, the boot
>>> process failed and I feel depressed.
>>>
>>> The LS7A bridge chip is used a lot with 3A3000 or 3A4000 CPU in
>>> the most Loongson desktop and sever products, it is important to
>>> support LS7A bridge chip by the Linux mainline kernel.
>>>
>>> This patch series adds the basic support for the LS7A bridge chip,
>>> the patch about vendor ID and SATA has been merged into the mainline
>>> tree, the next work is to refactor the code about the interrupt
>>> controller, and then power management and some other controller
>>> device drivers.
>>>
>>> By the way, if you want the boot process is successful (just for
>>> test) on the Loongson 3A3000 CPU and LS7A bridge chip system,
>>> you should not only apply these patches, but also need the support
>>> for SATA and interrupt controller in the v1 patch series.
>>>
>>> This patch series is based on mips-next.
>>>
>>> If you have any questions and suggestions, please let me know.
>>>
>>> Thanks,
>>>
>>> Tiezhu Yang
>>>
>>> v2:
>>> - The split patch series about Loongson vendor ID and SATA
>>> controller has been merged into the linux-block.git by Jens Axboe
>>> [1].
>>>
>>> - Think about using hierarchy IRQ domain in the patch of
>>> interrupt controller, and this maybe depend on the patch series by
>>> Jiaxun ("Modernize Loongson64 Machine"), so the patch about
>>> interrupt is not included in this v2 patch series.
>>>
>>> v3:
>>> - The split patch series about Loongson vendor ID and SATA
>>> controller has been merged into the mainline tree [2]
>>>
>>> - Modify the macro definition and add comment to make it easy to
>>> read
>>>
>>> - Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
>>>
>>> - Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
>>>
>>> v4:
>>> - Use LS7A instead of Loongson 7A1000 in the description
>>> - Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
>>>
>>> [1]
>>> https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=9acb9fe18d86
>>> https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=e49bd683e00b
>>> [2]
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e49bd683e00b
>>>
>>> Tiezhu Yang (3):
>>> MIPS: Loongson: Get host bridge information
>>> MIPS: Loongson: Add DMA support for LS7A
>>> MIPS: Loongson: Add PCI support for LS7A
>>>
>>> arch/mips/include/asm/mach-loongson64/boot_param.h | 20 +++++++
>>> arch/mips/loongson64/dma.c | 9 ++--
>>> arch/mips/loongson64/env.c | 22 ++++++++
>>> arch/mips/loongson64/init.c | 17 ++++++
>>> arch/mips/pci/fixup-loongson3.c | 12 +++++
>>> arch/mips/pci/ops-loongson3.c | 63
>>> ++++++++++++++++++++-- 6 files changed, 136 insertions(+), 7
>>> deletions(-)
>> Hi Thomas,
>>
>> Could you please apply the following two patches to mips-next?
>>
>> [v4,1/3] MIPS: Loongson: Get host bridge information
>> https://lore.kernel.org/patchwork/patch/1220009/
>>
>> [v4,2/3] MIPS: Loongson: Add DMA support for LS7A
>> https://lore.kernel.org/patchwork/patch/1220010/
> Sorry but I really don't like the DMA patch, hard coding a config
> register in platform code is not necessarily a good idea, it
> create painful hell for adding new platform support.
>
> I'm trying very hard to let all devices go through DeviceTree.
>
> I'd suggest you to limit DMA capability on LS7A PCH instead of doing
> the hack.
Hi Jiaxun,
Thanks for your suggestion, let me rethink how to properly support DMA.
Do you think the following patch could be applied first?
[v4,1/3] MIPS: Loongson: Get host bridge information
https://lore.kernel.org/patchwork/patch/1220009/
Thanks,
Tiezhu Yang
>
> Or if you think the function is necessary, you can create a DeviceTree
> node called "loongson,ls7a-syscon", and do whatever you like in
> init_calls by parsing this node.
>
> Also that will also block my upcoming LS2K support patches.
> You can check my tree here[1].
>
> Thanks.
>
> [1]: https://github.com/FlyGoat/linux/commits/next-testing-2k
>
>> Thanks,
>> Tiezhu Yang
>>
> --
> Jiaxun Yang
On Mon, 27 Apr 2020 13:42:06 +0800
Tiezhu Yang <[email protected]> wrote:
> On 04/27/2020 12:57 PM, Jiaxun Yang wrote:
> > On Mon, 27 Apr 2020 09:31:54 +0800
> > Tiezhu Yang <[email protected]> wrote:
> >
> >> On 04/03/2020 05:29 PM, Tiezhu Yang wrote:
> >>> The LS7A bridge chip has been released for several years since the
> >>> second half of 2017, but it is not supported by the Linux mainline
> >>> kernel while it only works well with the Loongson internal kernel
> >>> version. When I update the latest version of Linux mainline kernel
> >>> on the Loongson 3A3000 CPU and LS7A bridge chip system, the boot
> >>> process failed and I feel depressed.
> >>>
> >>> The LS7A bridge chip is used a lot with 3A3000 or 3A4000 CPU in
> >>> the most Loongson desktop and sever products, it is important to
> >>> support LS7A bridge chip by the Linux mainline kernel.
> >>>
> >>> This patch series adds the basic support for the LS7A bridge chip,
> >>> the patch about vendor ID and SATA has been merged into the
> >>> mainline tree, the next work is to refactor the code about the
> >>> interrupt controller, and then power management and some other
> >>> controller device drivers.
> >>>
> >>> By the way, if you want the boot process is successful (just for
> >>> test) on the Loongson 3A3000 CPU and LS7A bridge chip system,
> >>> you should not only apply these patches, but also need the support
> >>> for SATA and interrupt controller in the v1 patch series.
> >>>
> >>> This patch series is based on mips-next.
> >>>
> >>> If you have any questions and suggestions, please let me know.
> >>>
> >>> Thanks,
> >>>
> >>> Tiezhu Yang
> >>>
> >>> v2:
> >>> - The split patch series about Loongson vendor ID and SATA
> >>> controller has been merged into the linux-block.git by Jens Axboe
> >>> [1].
> >>>
> >>> - Think about using hierarchy IRQ domain in the patch of
> >>> interrupt controller, and this maybe depend on the patch series by
> >>> Jiaxun ("Modernize Loongson64 Machine"), so the patch about
> >>> interrupt is not included in this v2 patch series.
> >>>
> >>> v3:
> >>> - The split patch series about Loongson vendor ID and SATA
> >>> controller has been merged into the mainline tree [2]
> >>>
> >>> - Modify the macro definition and add comment to make it easy
> >>> to read
> >>>
> >>> - Move ls7a1000_pci_class_quirk() to fixup-loongson3.c
> >>>
> >>> - Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014
> >>>
> >>> v4:
> >>> - Use LS7A instead of Loongson 7A1000 in the description
> >>> - Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code
> >>>
> >>> [1]
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=9acb9fe18d86
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git/commit/?h=for-next&id=e49bd683e00b
> >>> [2]
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86
> >>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e49bd683e00b
> >>>
> >>> Tiezhu Yang (3):
> >>> MIPS: Loongson: Get host bridge information
> >>> MIPS: Loongson: Add DMA support for LS7A
> >>> MIPS: Loongson: Add PCI support for LS7A
> >>>
> >>> arch/mips/include/asm/mach-loongson64/boot_param.h | 20 +++++++
> >>> arch/mips/loongson64/dma.c | 9 ++--
> >>> arch/mips/loongson64/env.c | 22
> >>> ++++++++ arch/mips/loongson64/init.c | 17
> >>> ++++++ arch/mips/pci/fixup-loongson3.c | 12
> >>> +++++ arch/mips/pci/ops-loongson3.c | 63
> >>> ++++++++++++++++++++-- 6 files changed, 136 insertions(+), 7
> >>> deletions(-)
> >> Hi Thomas,
> >>
> >> Could you please apply the following two patches to mips-next?
> >>
> >> [v4,1/3] MIPS: Loongson: Get host bridge information
> >> https://lore.kernel.org/patchwork/patch/1220009/
> >>
> >> [v4,2/3] MIPS: Loongson: Add DMA support for LS7A
> >> https://lore.kernel.org/patchwork/patch/1220010/
> > Sorry but I really don't like the DMA patch, hard coding a config
> > register in platform code is not necessarily a good idea, it
> > create painful hell for adding new platform support.
> >
> > I'm trying very hard to let all devices go through DeviceTree.
> >
> > I'd suggest you to limit DMA capability on LS7A PCH instead of doing
> > the hack.
>
> Hi Jiaxun,
>
> Thanks for your suggestion, let me rethink how to properly support
> DMA.
>
> Do you think the following patch could be applied first?
>
> [v4,1/3] MIPS: Loongson: Get host bridge information
> https://lore.kernel.org/patchwork/patch/1220009/
Looks reasonable.
Thanks.
>
> Thanks,
> Tiezhu Yang
>
> >
> > Or if you think the function is necessary, you can create a
> > DeviceTree node called "loongson,ls7a-syscon", and do whatever you
> > like in init_calls by parsing this node.
> >
> > Also that will also block my upcoming LS2K support patches.
> > You can check my tree here[1].
> >
> > Thanks.
> >
> > [1]: https://github.com/FlyGoat/linux/commits/next-testing-2k
> >
> >> Thanks,
> >> Tiezhu Yang
> >>
> > --
> > Jiaxun Yang
>
--
Jiaxun Yang
On Mon, Apr 27, 2020 at 02:42:03PM +0800, Jiaxun Yang wrote:
> On Mon, 27 Apr 2020 13:42:06 +0800
> Tiezhu Yang <[email protected]> wrote:
> > Thanks for your suggestion, let me rethink how to properly support
> > DMA.
> >
> > Do you think the following patch could be applied first?
> >
> > [v4,1/3] MIPS: Loongson: Get host bridge information
> > https://lore.kernel.org/patchwork/patch/1220009/
>
> Looks reasonable.
>
> Thanks.
I've just applied the first patch of this series to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]