This add the DT bindings documentation for the Sparx5 SoC DPLL clock
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
.../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
new file mode 100644
index 0000000000000..594007d8fc59a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 DPLL Clock
+
+maintainers:
+ - Lars Povlsen <[email protected]>
+
+description: |
+ The Sparx5 DPLL clock controller generates and supplies clock to
+ various peripherals within the SoC.
+
+ This binding uses common clock bindings
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ const: microchip,sparx5-dpll
+
+ reg:
+ items:
+ - description: dpll registers
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock provider for eMMC:
+ - |
+ clks: clks@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ reg = <0x1110000c 0x24>;
+ };
+
+...
--
2.26.2
On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote:
> This add the DT bindings documentation for the Sparx5 SoC DPLL clock
>
> Reviewed-by: Alexandre Belloni <[email protected]>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
> new file mode 100644
> index 0000000000000..594007d8fc59a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Sparx5 DPLL Clock
> +
> +maintainers:
> + - Lars Povlsen <[email protected]>
> +
> +description: |
> + The Sparx5 DPLL clock controller generates and supplies clock to
> + various peripherals within the SoC.
> +
> + This binding uses common clock bindings
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +properties:
> + compatible:
> + const: microchip,sparx5-dpll
> +
> + reg:
> + items:
> + - description: dpll registers
For a single entry, just:
maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock provider for eMMC:
> + - |
> + clks: clks@61110000c {
clock-controller@1110000c {
> + compatible = "microchip,sparx5-dpll";
> + #clock-cells = <1>;
> + reg = <0x1110000c 0x24>;
Looks like this is a sub-block in some other h/w block. What's the
parent device? That should be described and this should be part of it
either as a single node or a child node. Without a complete view of what
this block has I can't provide any guidance.
Rob
Stephen Boyd writes:
> Quoting Lars Povlsen (2020-05-13 05:55:28)
>> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> new file mode 100644
>> index 0000000000000..594007d8fc59a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microchip Sparx5 DPLL Clock
>> +
>> +maintainers:
>> + - Lars Povlsen <[email protected]>
>> +
>> +description: |
>> + The Sparx5 DPLL clock controller generates and supplies clock to
>> + various peripherals within the SoC.
>> +
>> + This binding uses common clock bindings
>> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> I don't think we need this sentence. Please drop it.
OK. (Assuming the "This binding ..." part).
>
>> +
>> +properties:
>> + compatible:
>> + const: microchip,sparx5-dpll
>> +
>> + reg:
>> + items:
>> + - description: dpll registers
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + # Clock provider for eMMC:
>> + - |
>> + clks: clks@61110000c {
>
> Node name should be clock-controller@61110000c
Ok.
>
>> + compatible = "microchip,sparx5-dpll";
>> + #clock-cells = <1>;
>> + reg = <0x1110000c 0x24>;
>
> Does it consume any clks itself? I'd expect to see some sort of 'clocks'
> property in this node.
>
>> + };
I changed the driver to use a fixed-rate input clock, replacing the
BASE_CLOCK define(s). Additionally, I made the ahb_clock into
fixed-factor clock using the A53 cpu clock as a base.
So I updated the example and added 'clocks' to the schema.
I will send you a new series shortly.
Thank you for the comments.
--
Lars Povlsen,
Microchip
Rob Herring writes:
> On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote:
>> This add the DT bindings documentation for the Sparx5 SoC DPLL clock
>>
>> Reviewed-by: Alexandre Belloni <[email protected]>
>> Signed-off-by: Lars Povlsen <[email protected]>
>> ---
>> .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> new file mode 100644
>> index 0000000000000..594007d8fc59a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microchip Sparx5 DPLL Clock
>> +
>> +maintainers:
>> + - Lars Povlsen <[email protected]>
>> +
>> +description: |
>> + The Sparx5 DPLL clock controller generates and supplies clock to
>> + various peripherals within the SoC.
>> +
>> + This binding uses common clock bindings
>> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +properties:
>> + compatible:
>> + const: microchip,sparx5-dpll
>> +
>> + reg:
>> + items:
>> + - description: dpll registers
>
> For a single entry, just:
>
> maxItems: 1
Ok.
>
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + # Clock provider for eMMC:
>> + - |
>> + clks: clks@61110000c {
>
> clock-controller@1110000c {
>
Got that.
>> + compatible = "microchip,sparx5-dpll";
>> + #clock-cells = <1>;
>> + reg = <0x1110000c 0x24>;
>
> Looks like this is a sub-block in some other h/w block. What's the
> parent device? That should be described and this should be part of it
> either as a single node or a child node. Without a complete view of what
> this block has I can't provide any guidance.
No, as Alex noted to a similar comment in the temp. sensor driver, the
chip is using packed register spaces predominantly. So don't put too
much into the register offsets.
---Lars
>
> Rob
--
Lars Povlsen,
Microchip