This patch series adds support for Microchip Sparx5 SoC, the CPU
system of a advanced, TSN capable gigabit switch. The CPU is an armv8
x 2 CPU core (A53).
Although this is an ARM core, it shares some peripherals with the
Microsemi Ocelot SoC.
This is the first official revision of the series.
Lars Povlsen (14):
pinctrl: ocelot: Should register GPIO's even if not irq controller
pinctrl: ocelot: Remove instance number from pin functions
pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2
arm64: sparx5: Add support for Microchip 2xA53 SoC
dt-bindings: arm: sparx5: Add documentation for Microchip Sparx5 SoC
arm64: dts: sparx5: Add basic cpu support
dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support
arm64: dts: sparx5: Add pinctrl support
pinctrl: ocelot: Add Sparx5 SoC support
dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock
dt-bindings: clock: sparx5: Add bindings include file
clk: sparx5: Add Sparx5 SoC DPLL clock driver
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
arm64: dts: sparx5: Add i2c devices, i2c muxes
.../bindings/arm/microchip,sparx5.yaml | 87 +++
.../bindings/clock/microchip,sparx5-dpll.yaml | 46 ++
.../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 +-
MAINTAINERS | 9 +
arch/arm64/Kconfig.platforms | 14 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/microchip/Makefile | 4 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 202 +++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 21 +
.../boot/dts/microchip/sparx5_pcb134.dts | 17 +
.../dts/microchip/sparx5_pcb134_board.dtsi | 252 ++++++++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +
.../boot/dts/microchip/sparx5_pcb135.dts | 17 +
.../dts/microchip/sparx5_pcb135_board.dtsi | 92 +++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +
.../boot/dts/microchip/sparx5_pcb_common.dtsi | 19 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-sparx5.c | 269 +++++++++
drivers/pinctrl/pinctrl-ocelot.c | 558 +++++++++++++++---
include/dt-bindings/clock/microchip,sparx5.h | 23 +
20 files changed, 1587 insertions(+), 83 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
create mode 100644 arch/arm64/boot/dts/microchip/Makefile
create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
create mode 100644 drivers/clk/clk-sparx5.c
create mode 100644 include/dt-bindings/clock/microchip,sparx5.h
--
2.26.2
This patch removes the instance number from the "miim", "reco_clk" and
"sfp" pin function.
The change needed is to prepare the driver for adding new platforms
with more of these instances. The instance number is also redundant,
as this is implicit for each pin.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
drivers/pinctrl/pinctrl-ocelot.c | 94 ++++++++++----------------------
1 file changed, 30 insertions(+), 64 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index d4ac65b1efc0b..375f3ea3b80c4 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -46,32 +46,15 @@ enum {
FUNC_IRQ0_OUT,
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
- FUNC_MIIM1,
- FUNC_MIIM2,
+ FUNC_MIIM,
FUNC_PCI_WAKE,
FUNC_PTP0,
FUNC_PTP1,
FUNC_PTP2,
FUNC_PTP3,
FUNC_PWM,
- FUNC_RECO_CLK0,
- FUNC_RECO_CLK1,
- FUNC_SFP0,
- FUNC_SFP1,
- FUNC_SFP2,
- FUNC_SFP3,
- FUNC_SFP4,
- FUNC_SFP5,
- FUNC_SFP6,
- FUNC_SFP7,
- FUNC_SFP8,
- FUNC_SFP9,
- FUNC_SFP10,
- FUNC_SFP11,
- FUNC_SFP12,
- FUNC_SFP13,
- FUNC_SFP14,
- FUNC_SFP15,
+ FUNC_RECO_CLK,
+ FUNC_SFP,
FUNC_SG0,
FUNC_SG1,
FUNC_SG2,
@@ -92,32 +75,15 @@ static const char *const ocelot_function_names[] = {
[FUNC_IRQ0_OUT] = "irq0_out",
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
- [FUNC_MIIM1] = "miim1",
- [FUNC_MIIM2] = "miim2",
+ [FUNC_MIIM] = "miim",
[FUNC_PCI_WAKE] = "pci_wake",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
[FUNC_PTP2] = "ptp2",
[FUNC_PTP3] = "ptp3",
[FUNC_PWM] = "pwm",
- [FUNC_RECO_CLK0] = "reco_clk0",
- [FUNC_RECO_CLK1] = "reco_clk1",
- [FUNC_SFP0] = "sfp0",
- [FUNC_SFP1] = "sfp1",
- [FUNC_SFP2] = "sfp2",
- [FUNC_SFP3] = "sfp3",
- [FUNC_SFP4] = "sfp4",
- [FUNC_SFP5] = "sfp5",
- [FUNC_SFP6] = "sfp6",
- [FUNC_SFP7] = "sfp7",
- [FUNC_SFP8] = "sfp8",
- [FUNC_SFP9] = "sfp9",
- [FUNC_SFP10] = "sfp10",
- [FUNC_SFP11] = "sfp11",
- [FUNC_SFP12] = "sfp12",
- [FUNC_SFP13] = "sfp13",
- [FUNC_SFP14] = "sfp14",
- [FUNC_SFP15] = "sfp15",
+ [FUNC_RECO_CLK] = "reco_clk",
+ [FUNC_SFP] = "sfp",
[FUNC_SG0] = "sg0",
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
@@ -168,18 +134,18 @@ OCELOT_P(6, UART, TWI_SCL_M, NONE);
OCELOT_P(7, UART, TWI_SCL_M, NONE);
OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
-OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
-OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
-OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
-OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
-OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
-OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
+OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
+OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
+OCELOT_P(12, UART2, TWI_SCL_M, SFP);
+OCELOT_P(13, UART2, TWI_SCL_M, SFP);
+OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
+OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
OCELOT_P(16, TWI, NONE, SI);
OCELOT_P(17, TWI, TWI_SCL_M, SI);
OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
-OCELOT_P(20, RECO_CLK0, TACHO, NONE);
-OCELOT_P(21, RECO_CLK1, PWM, NONE);
+OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
+OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
#define OCELOT_PIN(n) { \
.number = n, \
@@ -264,22 +230,22 @@ JAGUAR2_P(40, NONE, TWI_SCL_M);
JAGUAR2_P(41, NONE, TWI_SCL_M);
JAGUAR2_P(42, NONE, TWI_SCL_M);
JAGUAR2_P(43, NONE, TWI_SCL_M);
-JAGUAR2_P(44, NONE, SFP8);
-JAGUAR2_P(45, NONE, SFP9);
-JAGUAR2_P(46, NONE, SFP10);
-JAGUAR2_P(47, NONE, SFP11);
-JAGUAR2_P(48, SFP0, NONE);
-JAGUAR2_P(49, SFP1, SI);
-JAGUAR2_P(50, SFP2, SI);
-JAGUAR2_P(51, SFP3, SI);
-JAGUAR2_P(52, SFP4, NONE);
-JAGUAR2_P(53, SFP5, NONE);
-JAGUAR2_P(54, SFP6, NONE);
-JAGUAR2_P(55, SFP7, NONE);
-JAGUAR2_P(56, MIIM1, SFP12);
-JAGUAR2_P(57, MIIM1, SFP13);
-JAGUAR2_P(58, MIIM2, SFP14);
-JAGUAR2_P(59, MIIM2, SFP15);
+JAGUAR2_P(44, NONE, SFP);
+JAGUAR2_P(45, NONE, SFP);
+JAGUAR2_P(46, NONE, SFP);
+JAGUAR2_P(47, NONE, SFP);
+JAGUAR2_P(48, SFP, NONE);
+JAGUAR2_P(49, SFP, SI);
+JAGUAR2_P(50, SFP, SI);
+JAGUAR2_P(51, SFP, SI);
+JAGUAR2_P(52, SFP, NONE);
+JAGUAR2_P(53, SFP, NONE);
+JAGUAR2_P(54, SFP, NONE);
+JAGUAR2_P(55, SFP, NONE);
+JAGUAR2_P(56, MIIM, SFP);
+JAGUAR2_P(57, MIIM, SFP);
+JAGUAR2_P(58, MIIM, SFP);
+JAGUAR2_P(59, MIIM, SFP);
JAGUAR2_P(60, NONE, NONE);
JAGUAR2_P(61, NONE, NONE);
JAGUAR2_P(62, NONE, NONE);
--
2.26.2
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option),
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/microchip/Makefile | 4 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 135 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb134.dts | 17 +++
.../dts/microchip/sparx5_pcb134_board.dtsi | 15 ++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb135.dts | 17 +++
.../dts/microchip/sparx5_pcb135_board.dtsi | 15 ++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++
.../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++
12 files changed, 271 insertions(+)
create mode 100644 arch/arm64/boot/dts/microchip/Makefile
create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b5a18d3dbb9f..5aa28d6e39d4f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2084,6 +2084,7 @@ M: Lars Povlsen <[email protected]>
M: Steen Hegelund <[email protected]>
M: Microchip Linux Driver Support <[email protected]>
L: [email protected] (moderated for non-subscribers)
+F: arch/arm64/boot/dts/microchip/
N: sparx5
S: Supported
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f19b762c008d8..9680a7f20c307 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -17,6 +17,7 @@ subdir-y += intel
subdir-y += lg
subdir-y += marvell
subdir-y += mediatek
+subdir-y += microchip
subdir-y += nvidia
subdir-y += qcom
subdir-y += realtek
diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile
new file mode 100644
index 0000000000000..c6e0313eea0f9
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
+dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
new file mode 100644
index 0000000000000..3136b4369f507
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "microchip,sparx5";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+ next-level-cache = <&L2_0>;
+ };
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+ next-level-cache = <&L2_0>;
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts =
+ <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clocks: clocks {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <625000000>;
+ };
+ };
+
+ axi: axi@600000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@600300000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ reg = <0x6 0x00300000 0x20000>, /* GICD */
+ <0x6 0x00340000 0x1000000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@600100000 {
+ compatible = "ns16550a";
+ reg = <0x6 0x00100000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@600102000 {
+ compatible = "ns16550a";
+ reg = <0x6 0x00102000 0x20>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ timer1: timer@600105000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x6 0x00105000 0x1000>;
+ clocks = <&ahb_clk>;
+ clock-names = "timer";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
new file mode 100644
index 0000000000000..d7f985f7ee020
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/ {
+ model = "Sparx5 PCB125 Reference Board";
+ compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
new file mode 100644
index 0000000000000..feee4e99ff57c
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
new file mode 100644
index 0000000000000..9b2aec400101b
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
new file mode 100644
index 0000000000000..10081a66961bb
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb134_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB134 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
new file mode 100644
index 0000000000000..20e409a9be196
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (NAND)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
new file mode 100644
index 0000000000000..9b2aec400101b
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb_common.dtsi"
+
+/{
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ priority = <200>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
new file mode 100644
index 0000000000000..741f0e12260e5
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5_pcb135_board.dtsi"
+
+/ {
+ model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
+ compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x10000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
new file mode 100644
index 0000000000000..1f99d0db1284f
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+#include "sparx5.dtsi"
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
2.26.2
The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
include/dt-bindings/clock/microchip,sparx5.h | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 include/dt-bindings/clock/microchip,sparx5.h
diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h
new file mode 100644
index 0000000000000..4b04dabacec2c
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,sparx5.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 Microchip Inc.
+ *
+ * Author: Lars Povlsen <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SPARX5_H
+#define _DT_BINDINGS_CLK_SPARX5_H
+
+#define CLK_ID_CORE 0
+#define CLK_ID_DDR 1
+#define CLK_ID_CPU2 2
+#define CLK_ID_ARM2 3
+#define CLK_ID_AUX1 4
+#define CLK_ID_AUX2 5
+#define CLK_ID_AUX3 6
+#define CLK_ID_AUX4 7
+#define CLK_ID_SYNCE 8
+
+#define N_CLOCKS 9
+
+#endif
--
2.26.2
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <[email protected]> wrote:
> This patch removes the instance number from the "miim", "reco_clk" and
> "sfp" pin function.
>
> The change needed is to prepare the driver for adding new platforms
> with more of these instances. The instance number is also redundant,
> as this is implicit for each pin.
>
> Reviewed-by: Alexandre Belloni <[email protected]>
> Signed-off-by: Lars Povlsen <[email protected]>
This patch applied to the pinctrl tree.
Yours,
Linus Walleij
On Wed, May 13, 2020 at 2:55 PM Lars Povlsen <[email protected]> wrote:
>
> This patch series adds support for Microchip Sparx5 SoC, the CPU
> system of a advanced, TSN capable gigabit switch. The CPU is an armv8
> x 2 CPU core (A53).
>
> Although this is an ARM core, it shares some peripherals with the
> Microsemi Ocelot SoC.
>
> This is the first official revision of the series.
I see you sent multiple series to [email protected] for review. This is the
correct address for getting the initial soc support merged, but as the patches
are still being reviewed by subsystem maintainers, please leave it off
for now, until you are confident that they are ready to get merged for the
following merge window and have received the appropriate Acks.
For each subsystem, there is generally the choice between merging
code through the subsystem maintainer tree, or through the soc tree
on an initial submission, as going through multiple trees is particularly
hard to do for the devicetree files.
For the moment, I have marked all sparx5 patches as "Not Applicable"
in patchwork at https://patchwork.kernel.org/project/linux-soc/list/
as it is still unclear who is merging which parts, and they are under
active review, but please do send them again after the review is
complete.
If you have a lot of patches, sending pull requests is sometimes easier,
but it also takes a bit of practice to know how exactly to structure
those. Let me know if you have questions about them. You an also
contact me and most of the other maintainers on IRC using the
#armlinux channel on irc.freenode.net.
Sorry for not having been able to review the patches myself yet, I
hope to get to that soon.
Arnd