This add DT bindings for the Microsemi/Microchip SPI controller used
in various SoC's. It describes the "mscc,ocelot-spi" and
"mscc,jaguar2-spi" bindings.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
.../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++
.../bindings/spi/snps,dw-apb-ssi.txt | 7 +--
MAINTAINERS | 1 +
3 files changed, 63 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
new file mode 100644
index 0000000000000..a3ac0fa576553
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/mscc,ocelot-spi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Vcore-III SPI Communication Controller
+
+maintainers:
+ - Alexandre Belloni <[email protected]>
+ - Lars Povlsen <[email protected]>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+description: |
+ The Microsemi Vcore-III SPI controller is a general purpose SPI
+ controller based upon the Designware SPI controller. It uses an 8
+ byte rx/tx fifo.
+
+properties:
+ compatible:
+ enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ minItems: 2
+ items:
+ - description: Designware SPI registers
+ - description: CS override registers
+
+ clocks:
+ maxItems: 1
+
+ reg-io-width:
+ description: |
+ The I/O register width (in bytes) implemented by this device.
+ items:
+ enum: [ 2, 4 ]
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ spi0: spi@101000 {
+ compatible = "mscc,ocelot-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x101000 0x100>, <0x3c 0x18>;
+ interrupts = <9>;
+ clocks = <&ahb_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 3ed08ee9feba4..5e1849be7bae5 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,10 +1,8 @@
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi"
-- reg : The register base for the controller. For "mscc,<soc>-spi", a second
- register set is required (named ICPU_CFG:SPI_MST)
+- compatible : "snps,dw-apb-ssi" or "amazon,alpine-dw-apb-ssi"
+- reg : The register base for the controller.
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
@@ -38,4 +36,3 @@ Example:
cs-gpios = <&gpio0 13 0>,
<&gpio0 14 0>;
};
-
diff --git a/MAINTAINERS b/MAINTAINERS
index 1db598723a1d8..6472240b8391b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11231,6 +11231,7 @@ L: [email protected]
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.26.2
On 13/05/20 15:52, Mark Brown wrote:
> Date: Wed, 13 May 2020 15:52:13 +0100
> From: Mark Brown <[email protected]>
> To: Lars Povlsen <[email protected]>
> Cc: SoC Team <[email protected]>, Rob Herring <[email protected]>, Microchip
> Linux Driver Support <[email protected]>,
> [email protected], [email protected],
> [email protected], [email protected],
> Alexandre Belloni <[email protected]>, Serge Semin
> <[email protected]>, Serge Semin
> <[email protected]>, Andy Shevchenko
> <[email protected]>, Wan Ahmad Zainie
> <[email protected]>
> Subject: Re: [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp
> User-Agent: Mutt/1.10.1 (2018-07-13)
>
> On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote:
> > This add DT bindings for the Microsemi/Microchip SPI controller used
> > in various SoC's. It describes the "mscc,ocelot-spi" and
> > "mscc,jaguar2-spi" bindings.
>
> > Reviewed-by: Alexandre Belloni <[email protected]>
> > Signed-off-by: Lars Povlsen <[email protected]>
> > ---
> > .../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++
> > .../bindings/spi/snps,dw-apb-ssi.txt | 7 +--
>
> That's not what this change does. It is removing the existing binding
> for Ocelot and Jaguar2 from the free format binding documentation and
> adds some entirely separate YAML bindings for them. This conflicts with
> competing YAML conversions that both Serge Semin and Wan Ahmad Zainie
> (CCed) have in flight at the minute. It also doesn't strike me as a
> good idea to fork the bindings, what's the motivation for doing that?
The reason for doing this was due to the fact that I felt adding
Sparx5 support only cluttered the original driver even more.
And since I was adding a new driver, I needed to add bindings for it -
and (re)move the old ones.
I have become aware of Serge and Wan Ahmad's work, and will work out
something on top of that.
On 19/05/20 12:58, Mark Brown wrote:
> Date: Tue, 19 May 2020 12:58:29 +0100
> From: Mark Brown <[email protected]>
> To: Lars Povlsen <[email protected]>
> Cc: SoC Team <[email protected]>, Rob Herring <[email protected]>, Microchip
> Linux Driver Support <[email protected]>,
> [email protected], [email protected],
> [email protected], [email protected],
> Alexandre Belloni <[email protected]>, Serge Semin
> <[email protected]>, Serge Semin
> <[email protected]>, Andy Shevchenko
> <[email protected]>, Wan Ahmad Zainie
> <[email protected]>
> Subject: Re: [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp
> User-Agent: Mutt/1.10.1 (2018-07-13)
>
> On Tue, May 19, 2020 at 01:47:39PM +0200, Lars Povlsen wrote:
> > On 13/05/20 15:52, Mark Brown wrote:
>
> > > On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote:
> > > > This add DT bindings for the Microsemi/Microchip SPI controller used
> > > > in various SoC's. It describes the "mscc,ocelot-spi" and
> > > > "mscc,jaguar2-spi" bindings.
>
> > > That's not what this change does. It is removing the existing binding
> > > for Ocelot and Jaguar2 from the free format binding documentation and
>
> > The reason for doing this was due to the fact that I felt adding
> > Sparx5 support only cluttered the original driver even more.
>
> That's not the issue I'm pointing out there. The issue is that your
> changelog claims that the change does one thing and the change itself
> does something substantially different.
Ok, got it. I'll reword the changelog to be more precise.
Thanks again,
---Lars
On Wed, May 13, 2020 at 04:00:25PM +0200, Lars Povlsen wrote:
> This add DT bindings for the Microsemi/Microchip SPI controller used
> in various SoC's. It describes the "mscc,ocelot-spi" and
> "mscc,jaguar2-spi" bindings.
As I see it, there is no need in this patch at all. Current DT binding file
describes the MSCC version of the DW APB SSI IP pretty well. You can add an
example to the DT schema though with "mscc,ocelot-spi" or "mscc,jaguar2-spi"
compatible string and additional registers range.
-Sergey
>
> Reviewed-by: Alexandre Belloni <[email protected]>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++
> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +--
> MAINTAINERS | 1 +
> 3 files changed, 63 insertions(+), 5 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> new file mode 100644
> index 0000000000000..a3ac0fa576553
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/mscc,ocelot-spi.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microsemi Vcore-III SPI Communication Controller
> +
> +maintainers:
> + - Alexandre Belloni <[email protected]>
> + - Lars Povlsen <[email protected]>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +description: |
> + The Microsemi Vcore-III SPI controller is a general purpose SPI
> + controller based upon the Designware SPI controller. It uses an 8
> + byte rx/tx fifo.
> +
> +properties:
> + compatible:
> + enum:
> + - mscc,ocelot-spi
> + - mscc,jaguar2-spi
> +
> + interrupts:
> + maxItems: 1
> +
> + reg:
> + minItems: 2
> + items:
> + - description: Designware SPI registers
> + - description: CS override registers
> +
> + clocks:
> + maxItems: 1
> +
> + reg-io-width:
> + description: |
> + The I/O register width (in bytes) implemented by this device.
> + items:
> + enum: [ 2, 4 ]
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +examples:
> + - |
> + spi0: spi@101000 {
> + compatible = "mscc,ocelot-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x101000 0x100>, <0x3c 0x18>;
> + interrupts = <9>;
> + clocks = <&ahb_clk>;
> + };
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> index 3ed08ee9feba4..5e1849be7bae5 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> @@ -1,10 +1,8 @@
> Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
>
> Required properties:
> -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
> - "jaguar2", or "amazon,alpine-dw-apb-ssi"
> -- reg : The register base for the controller. For "mscc,<soc>-spi", a second
> - register set is required (named ICPU_CFG:SPI_MST)
> +- compatible : "snps,dw-apb-ssi" or "amazon,alpine-dw-apb-ssi"
> +- reg : The register base for the controller.
> - interrupts : One interrupt, used by the controller.
> - #address-cells : <1>, as required by generic SPI binding.
> - #size-cells : <0>, also as required by generic SPI binding.
> @@ -38,4 +36,3 @@ Example:
> cs-gpios = <&gpio0 13 0>,
> <&gpio0 14 0>;
> };
> -
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1db598723a1d8..6472240b8391b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11231,6 +11231,7 @@ L: [email protected]
> S: Supported
> F: Documentation/devicetree/bindings/mips/mscc.txt
> F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> +F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> F: arch/mips/boot/dts/mscc/
> F: arch/mips/configs/generic/board-ocelot.config
> F: arch/mips/generic/board-ocelot.c
> --
> 2.26.2
>
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