This is an add-on series to the main SoC Sparx5 series
(Message-ID: <[email protected]>).
The series add support for Sparx5 on top of the existing
ocelot/jaguar2 spi driver.
It spins off the existing support for the MSCC platforms into a
separate driver, as adding new platforms from the MSCC/Microchip
product lines will further complicate (clutter) the original driver.
New YAML dt-bindings are provided for the resulting driver.
It is expected that the DT patches are to be taken directly by the arm-soc
maintainers.
Lars Povlsen (10):
spi: dw: Add support for polled operation via no IRQ specified in DT
spi: dw: Add support for RX sample delay register
spi: dw: Add support for client driver memory operations
dt-bindings: spi: Add bindings for spi-dw-mchp
spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
spi: spi-dw-mchp: Add Sparx5 support
arm64: dts: sparx5: Add SPI controller
arm64: dts: sparx5: Add spi-nor support
arm64: dts: sparx5: Add spi-nand devices
.../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++
.../bindings/spi/snps,dw-apb-ssi.txt | 7 +-
MAINTAINERS | 2 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 16 +
.../boot/dts/microchip/sparx5_pcb134.dts | 22 +
.../dts/microchip/sparx5_pcb134_board.dtsi | 9 +
.../boot/dts/microchip/sparx5_pcb135.dts | 23 +
.../dts/microchip/sparx5_pcb135_board.dtsi | 9 +
arch/mips/configs/generic/board-ocelot.config | 2 +-
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++
drivers/spi/spi-dw-mmio.c | 93 ----
drivers/spi/spi-dw.c | 31 +-
drivers/spi/spi-dw.h | 4 +
16 files changed, 644 insertions(+), 107 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
create mode 100644 drivers/spi/spi-dw-mchp.c
--
2.26.2
This minor change allow dw-spi drivers to register
spi_controller_mem_ops memory operations if the platform supports it.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
drivers/spi/spi-dw.c | 3 +++
drivers/spi/spi-dw.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 32997f28fa5bb..d0c611c42421e 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -527,6 +527,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
/* Basic HW init */
spi_hw_init(dev, dws);
+ /* Memory ops? */
+ master->mem_ops = dws->mem_ops;
+
if (dws->dma_ops && dws->dma_ops->dma_init) {
ret = dws->dma_ops->dma_init(dws);
if (ret) {
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index ed6e47b3f50da..8ecccbde10a20 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -3,6 +3,7 @@
#define DW_SPI_HEADER_H
#include <linux/io.h>
+#include <linux/spi/spi-mem.h>
#include <linux/scatterlist.h>
/* Register offsets */
@@ -116,6 +117,7 @@ struct dw_spi {
u16 bus_num;
u16 num_cs; /* supported slave numbers */
void (*set_cs)(struct spi_device *spi, bool enable);
+ const struct spi_controller_mem_ops *mem_ops;
/* Current message transfer state info */
size_t len;
--
2.26.2
This patch spins off the MSCC platforms into a separate driver, as
adding new platforms from the MSCC/Microchip product lines will
further complicate (clutter) the original driver.
The new 'spi-dw-mchp' driver still builds on the dw-spi foundation.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
MAINTAINERS | 1 +
arch/mips/configs/generic/board-ocelot.config | 2 +-
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-dw-mchp.c | 232 ++++++++++++++++++
drivers/spi/spi-dw-mmio.c | 93 -------
6 files changed, 242 insertions(+), 94 deletions(-)
create mode 100644 drivers/spi/spi-dw-mchp.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 6472240b8391b..de64fd4548697 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2085,6 +2085,7 @@ M: Steen Hegelund <[email protected]>
M: Microchip Linux Driver Support <[email protected]>
L: [email protected] (moderated for non-subscribers)
F: arch/arm64/boot/dts/microchip/
+F: drivers/spi/spi-dw-mchp.c
N: sparx5
S: Supported
diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
index 7626f2a75b03f..6dbae76268a49 100644
--- a/arch/mips/configs/generic/board-ocelot.config
+++ b/arch/mips/configs/generic/board-ocelot.config
@@ -38,7 +38,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DESIGNWARE=y
-CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_DW_MCHP=y
CONFIG_SPI_SPIDEV=y
CONFIG_PINCTRL=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 741b9140992a8..77eb580b9f51f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -238,6 +238,13 @@ config SPI_DW_MMIO
tristate "Memory-mapped io interface driver for DW SPI core"
depends on SPI_DESIGNWARE
+config SPI_DW_MCHP
+ tristate "Memory-mapped io interface driver using DW SPI core of MSCC SoCs"
+ default y if ARCH_SPARX5
+ default y if SOC_VCOREIII
+ select SPI_DESIGNWARE
+ select SPI_DW_MMIO
+
config SPI_DLN2
tristate "Diolan DLN-2 USB SPI adapter"
depends on MFD_DLN2
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 28f601327f8c7..be8a52d90721b 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
+obj-$(CONFIG_SPI_DW_MCHP) += spi-dw-mchp.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
diff --git a/drivers/spi/spi-dw-mchp.c b/drivers/spi/spi-dw-mchp.c
new file mode 100644
index 0000000000000..0828a7616d9ab
--- /dev/null
+++ b/drivers/spi/spi-dw-mchp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Memory-mapped interface driver for MSCC SoCs
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/spi/spi-mem.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include "spi-dw.h"
+
+#define DRIVER_NAME "dw_spi_mchp"
+
+#define MAX_CS 4
+
+#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
+#define OCELOT_IF_SI_OWNER_OFFSET 4
+#define JAGUAR2_IF_SI_OWNER_OFFSET 6
+#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
+#define MSCC_IF_SI_OWNER_SISL 0
+#define MSCC_IF_SI_OWNER_SIBM 1
+#define MSCC_IF_SI_OWNER_SIMC 2
+
+#define MSCC_SPI_MST_SW_MODE 0x14
+#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
+#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
+
+struct dw_spi_mchp_props {
+ const char *syscon_name;
+ u32 si_owner_bit;
+};
+
+struct dw_spi_mchp {
+ struct dw_spi dws;
+ struct clk *clk;
+ void __iomem *read_map;
+ struct regmap *syscon;
+ void __iomem *spi_mst;
+ const struct dw_spi_mchp_props *props;
+ u32 gen_owner;
+};
+
+static const struct dw_spi_mchp_props dw_spi_mchp_props_ocelot = {
+ .syscon_name = "mscc,ocelot-cpu-syscon",
+ .si_owner_bit = 4,
+};
+
+static const struct dw_spi_mchp_props dw_spi_mchp_props_jaguar2 = {
+ .syscon_name = "mscc,ocelot-cpu-syscon",
+ .si_owner_bit = 6,
+};
+
+/*
+ * The Designware SPI controller (referred to as master in the documentation)
+ * automatically deasserts chip select when the tx fifo is empty. The chip
+ * selects then needs to be either driven as GPIOs or, for the first 4 using the
+ * the SPI boot controller registers. the final chip select is an OR gate
+ * between the Designware SPI controller and the SPI boot controller.
+ */
+static void dw_spi_mchp_set_cs(struct spi_device *spi, bool enable)
+{
+ struct dw_spi *dws = spi_master_get_devdata(spi->master);
+ struct dw_spi_mchp *dwsmchp = container_of(dws, struct dw_spi_mchp,
+ dws);
+ u32 cs = spi->chip_select;
+
+ if (cs < 4) {
+ u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
+
+ if (!enable)
+ sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
+
+ writel(sw_mode, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE);
+ }
+
+ dw_spi_set_cs(spi, enable);
+}
+
+static int dw_spi_mchp_init(struct platform_device *pdev,
+ struct dw_spi *dws,
+ struct dw_spi_mchp *dwsmchp,
+ const struct dw_spi_mchp_props *props)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (res && resource_size(res) > 0) {
+ dwsmchp->spi_mst = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(dwsmchp->spi_mst)) {
+ dev_err(&pdev->dev, "SPI_MST region map failed\n");
+ return PTR_ERR(dwsmchp->spi_mst);
+ }
+ }
+
+ dwsmchp->syscon =
+ syscon_regmap_lookup_by_compatible(props->syscon_name);
+ if (IS_ERR(dwsmchp->syscon)) {
+ dev_err(&pdev->dev, "No syscon map %s\n", props->syscon_name);
+ return PTR_ERR(dwsmchp->syscon);
+ }
+ dwsmchp->props = props;
+
+ /* Deassert all CS */
+ if (dwsmchp->spi_mst)
+ writel(0, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE);
+
+ /* Select the owner of the SI interface */
+ regmap_update_bits(dwsmchp->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
+ MSCC_IF_SI_OWNER_MASK << props->si_owner_bit,
+ MSCC_IF_SI_OWNER_SIMC << props->si_owner_bit);
+
+ dwsmchp->dws.set_cs = dw_spi_mchp_set_cs;
+
+ return 0;
+}
+
+static int dw_spi_mchp_probe(struct platform_device *pdev)
+{
+ const struct dw_spi_mchp_props *props;
+ struct dw_spi_mchp *dwsmchp;
+ struct dw_spi *dws;
+ int ret;
+ int num_cs, rx_sample_dly;
+
+ dwsmchp = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mchp),
+ GFP_KERNEL);
+ if (!dwsmchp)
+ return -ENOMEM;
+
+ dws = &dwsmchp->dws;
+
+ /* Get basic io resource and map it */
+ dws->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dws->regs)) {
+ dev_err(&pdev->dev, "SPI region map failed\n");
+ return PTR_ERR(dws->regs);
+ }
+
+ dws->irq = of_irq_get(pdev->dev.of_node, 0);
+ if (dws->irq < 0)
+ dev_info(&pdev->dev, "no irq, using polled mode\n");
+
+ dwsmchp->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(dwsmchp->clk))
+ return PTR_ERR(dwsmchp->clk);
+ ret = clk_prepare_enable(dwsmchp->clk);
+ if (ret)
+ return ret;
+
+ dws->bus_num = pdev->id;
+
+ dws->max_freq = clk_get_rate(dwsmchp->clk);
+
+ device_property_read_u32(&pdev->dev, "reg-io-width",
+ &dws->reg_io_width);
+
+ num_cs = MAX_CS;
+
+ device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
+
+ dws->num_cs = num_cs;
+
+ rx_sample_dly = 0;
+ device_property_read_u32(&pdev->dev, "spi-rx-delay-us", &rx_sample_dly);
+ dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly,
+ (dws->max_freq / 1000000));
+
+ props = device_get_match_data(&pdev->dev);
+ if (props)
+ ret = dw_spi_mchp_init(pdev, dws, dwsmchp, props);
+ else
+ ret = -EINVAL;
+ if (ret)
+ goto out;
+
+ ret = dw_spi_add_host(&pdev->dev, dws);
+ if (ret)
+ goto out;
+
+ platform_set_drvdata(pdev, dwsmchp);
+ return 0;
+
+out:
+ clk_disable_unprepare(dwsmchp->clk);
+ return ret;
+}
+
+static int dw_spi_mchp_remove(struct platform_device *pdev)
+{
+ struct dw_spi_mchp *dwsmchp = platform_get_drvdata(pdev);
+
+ dw_spi_remove_host(&dwsmchp->dws);
+ clk_disable_unprepare(dwsmchp->clk);
+
+ return 0;
+}
+
+static const struct of_device_id dw_spi_mchp_of_match[] = {
+ { .compatible = "mscc,ocelot-spi", .data = &dw_spi_mchp_props_ocelot},
+ { .compatible = "mscc,jaguar2-spi", .data = &dw_spi_mchp_props_jaguar2},
+ { /* end of table */}
+};
+MODULE_DEVICE_TABLE(of, dw_spi_mchp_of_match);
+
+static struct platform_driver dw_spi_mchp_driver = {
+ .probe = dw_spi_mchp_probe,
+ .remove = dw_spi_mchp_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = dw_spi_mchp_of_match,
+ },
+};
+module_platform_driver(dw_spi_mchp_driver);
+
+MODULE_AUTHOR("Lars Povlsen <[email protected]>");
+MODULE_DESCRIPTION("Memory-mapped I/O interface DW SPI driver for MSCC SoCs");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d0..dc5db548fbcbc 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -32,97 +32,6 @@ struct dw_spi_mmio {
void *priv;
};
-#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
-#define OCELOT_IF_SI_OWNER_OFFSET 4
-#define JAGUAR2_IF_SI_OWNER_OFFSET 6
-#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
-#define MSCC_IF_SI_OWNER_SISL 0
-#define MSCC_IF_SI_OWNER_SIBM 1
-#define MSCC_IF_SI_OWNER_SIMC 2
-
-#define MSCC_SPI_MST_SW_MODE 0x14
-#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
-#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
-
-struct dw_spi_mscc {
- struct regmap *syscon;
- void __iomem *spi_mst;
-};
-
-/*
- * The Designware SPI controller (referred to as master in the documentation)
- * automatically deasserts chip select when the tx fifo is empty. The chip
- * selects then needs to be either driven as GPIOs or, for the first 4 using the
- * the SPI boot controller registers. the final chip select is an OR gate
- * between the Designware SPI controller and the SPI boot controller.
- */
-static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
-{
- struct dw_spi *dws = spi_master_get_devdata(spi->master);
- struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
- struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
- u32 cs = spi->chip_select;
-
- if (cs < 4) {
- u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
-
- if (!enable)
- sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
-
- writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
- }
-
- dw_spi_set_cs(spi, enable);
-}
-
-static int dw_spi_mscc_init(struct platform_device *pdev,
- struct dw_spi_mmio *dwsmmio,
- const char *cpu_syscon, u32 if_si_owner_offset)
-{
- struct dw_spi_mscc *dwsmscc;
-
- dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
- if (!dwsmscc)
- return -ENOMEM;
-
- dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(dwsmscc->spi_mst)) {
- dev_err(&pdev->dev, "SPI_MST region map failed\n");
- return PTR_ERR(dwsmscc->spi_mst);
- }
-
- dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
- if (IS_ERR(dwsmscc->syscon))
- return PTR_ERR(dwsmscc->syscon);
-
- /* Deassert all CS */
- writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
-
- /* Select the owner of the SI interface */
- regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
- MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
- MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
-
- dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
- dwsmmio->priv = dwsmscc;
-
- return 0;
-}
-
-static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
- struct dw_spi_mmio *dwsmmio)
-{
- return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
- OCELOT_IF_SI_OWNER_OFFSET);
-}
-
-static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
- struct dw_spi_mmio *dwsmmio)
-{
- return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
- JAGUAR2_IF_SI_OWNER_OFFSET);
-}
-
static int dw_spi_alpine_init(struct platform_device *pdev,
struct dw_spi_mmio *dwsmmio)
{
@@ -225,8 +134,6 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "snps,dw-apb-ssi", },
- { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
- { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
{ .compatible = "renesas,rzn1-spi", },
{ /* end of table */}
--
2.26.2
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++++
.../boot/dts/microchip/sparx5_pcb134.dts | 22 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb135.dts | 23 +++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 330fd8b096d4c..60629861a5157 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -193,6 +193,26 @@ gpio: pinctrl@6110101e0 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ si2_pins: si2-pins {
+ pins = "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "si2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index d8b5d23abfab0..94c4c3fd5a786 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -46,6 +46,13 @@ spi-flash@0 {
spi-max-frequency = <8000000>; /* input clock */
reg = <0>; /* CS0 */
};
+ spi-flash@1 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs1_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <8000000>;
+ reg = <1>; /* CS1 */
+ };
};
&i2c1 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
index feee4e99ff57c..9e8dc725a954a 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -15,3 +15,25 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */
+ spi-rx-delay-us = <500>; /* Tune for speed */
+ /* Dedicated SPI2 interface */
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
index 20e409a9be196..a31e10911dbaf 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -15,3 +15,26 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */
+ spi-rx-delay-us = <500>; /* Tune for speed */
+ /* Dedicated SPI2 interface */
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ };
+};
--
2.26.2
This add spi-nor device nodes to the Sparx5 reference boards.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++--
arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 9 +++++++++
arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 9 +++++++++
arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 9 +++++++++
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index daa216978887d..330fd8b096d4c 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -155,8 +155,9 @@ spi0: spi@600104000 {
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&ahb_clk>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-
+ /* NB: Polled mode - next line commented out
+ * interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ */
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index 573309fe45823..d8b5d23abfab0 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -39,6 +39,15 @@ &sdhci0 {
microchip,clock-delay = <10>;
};
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ };
+};
+
&i2c1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 18a535a043686..628a05d3f57ce 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -38,6 +38,15 @@ gpio-restart {
};
};
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
+ };
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index d71f11a10b3d2..fb0bc3b241204 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -51,6 +51,15 @@ i2cmux_s32: i2cmux-3 {
};
};
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
+ };
+};
+
&axi {
i2c0_imux: i2c0-imux@0 {
compatible = "i2c-mux-pinctrl";
--
2.26.2
This add DT bindings for the Sparx5 SPI driver.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
.../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++----
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
index a3ac0fa576553..8beecde4b0880 100644
--- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
@@ -23,15 +23,23 @@ properties:
enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
+ - microchip,sparx5-spi
interrupts:
maxItems: 1
reg:
minItems: 2
- items:
- - description: Designware SPI registers
- - description: CS override registers
+ maxItems: 3
+ oneOf:
+ - items:
+ - description: Designware SPI registers
+ - description: CS override registers (Not sparx5).
+ - items:
+ - description: Designware SPI registers
+ - description: CS override registers (Not sparx5).
+ - description: Direct mapped SPI read area. If provided, the
+ driver will register spi_mem_op's to take advantage of it.
clocks:
maxItems: 1
@@ -43,6 +51,23 @@ properties:
enum: [ 2, 4 ]
maxItems: 1
+ spi-rx-delay-us:
+ description: |
+ The delay (in usec) of the RX signal sample position. This can
+ be used to tne the RX timing in order to acheive higher
+ speeds. This is used for all devices on the bus.
+ default: 0
+ maxItems: 1
+
+ interface-mapping-mask:
+ description: |
+ On the Sparx5 variant, two different busses are connected to the
+ controller. This property is a mask per chip-select, indicating
+ whether the CS should go to one or the other interface.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ maxItems: 1
+
required:
- compatible
- reg
@@ -50,11 +75,15 @@ required:
examples:
- |
- spi0: spi@101000 {
- compatible = "mscc,ocelot-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x101000 0x100>, <0x3c 0x18>;
- interrupts = <9>;
- clocks = <&ahb_clk>;
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ spi0: spi@600104000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-spi";
+ reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>;
+ num-cs = <16>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.26.2
On 13/05/20 16:18, Mark Brown wrote:
> Date: Wed, 13 May 2020 16:18:11 +0100
> From: Mark Brown <[email protected]>
> To: Lars Povlsen <[email protected]>
> Cc: SoC Team <[email protected]>, Microchip Linux Driver Support
> <[email protected]>, [email protected],
> [email protected], [email protected],
> [email protected], Alexandre Belloni
> <[email protected]>
> Subject: Re: [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into
> spi-dw-mchp
> User-Agent: Mutt/1.10.1 (2018-07-13)
>
> On Wed, May 13, 2020 at 04:00:26PM +0200, Lars Povlsen wrote:
>
> > +config SPI_DW_MCHP
> > + tristate "Memory-mapped io interface driver using DW SPI core of MSCC SoCs"
> > + default y if ARCH_SPARX5
> > + default y if SOC_VCOREIII
>
> Why the default ys?
The SoC will typically boot from SPI... But its not a requirement per
se. I will remove it.
>
> > +++ b/drivers/spi/Makefile
> > @@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
> > obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
> > obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
> > obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
> > +obj-$(CONFIG_SPI_DW_MCHP) += spi-dw-mchp.o
> > obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
> > spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
> > obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
>
> Please keep the file alphabetically sorted.
>
Noted.
> > +++ b/drivers/spi/spi-dw-mchp.c
> > @@ -0,0 +1,232 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Memory-mapped interface driver for MSCC SoCs
> > + *
>
> Please make the entire comment a C++ one so things look more
> intentional.
Sure, I can do that. The presented form matches that of the other
spi-dw-* drivers, but I can see other using // blocks. Ack.
>
> > +#define MAX_CS 4
>
> This should be namespaced.
Ack.
>
> > + rx_sample_dly = 0;
> > + device_property_read_u32(&pdev->dev, "spi-rx-delay-us", &rx_sample_dly);
> > + dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly,
> > + (dws->max_freq / 1000000));
>
> If this is a standard feature of the DesignWare IP why parse it here and
> not in the generic code?
This is a standard feature of the DesignWare IP, so good suggestion. I
will arrange with Serge.
Thank you for your comments!
---Lars
Hello Lars,
On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> This is an add-on series to the main SoC Sparx5 series
> (Message-ID: <[email protected]>).
>
> The series add support for Sparx5 on top of the existing
> ocelot/jaguar2 spi driver.
>
> It spins off the existing support for the MSCC platforms into a
> separate driver, as adding new platforms from the MSCC/Microchip
> product lines will further complicate (clutter) the original driver.
>
> New YAML dt-bindings are provided for the resulting driver.
>
> It is expected that the DT patches are to be taken directly by the arm-soc
> maintainers.
Regarding our cooperation. It can be implemented as follows. Since your patchset
is less cumbersome than mine and is more ready to be integrated into the generic DW
APB SSI code, it would be better to first make it through Mark', Andy' and my reviews
to be further merged into the kernel version of the driver. After that I'll have
my code altered so it could be applied on top of your patches. When everything
is done we'll have a more comprehensive DW APB SSI driver with poll-based
PIO operations support, new features like rx-delay, etc.
Thank you one more time for the series you've shared with us. Let's see what can
be done to improve it...
-Sergey
>
> Lars Povlsen (10):
> spi: dw: Add support for polled operation via no IRQ specified in DT
> spi: dw: Add support for RX sample delay register
> spi: dw: Add support for client driver memory operations
> dt-bindings: spi: Add bindings for spi-dw-mchp
> spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
> dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
> spi: spi-dw-mchp: Add Sparx5 support
> arm64: dts: sparx5: Add SPI controller
> arm64: dts: sparx5: Add spi-nor support
> arm64: dts: sparx5: Add spi-nand devices
>
> .../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++
> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-
> MAINTAINERS | 2 +
> arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++
> .../boot/dts/microchip/sparx5_pcb125.dts | 16 +
> .../boot/dts/microchip/sparx5_pcb134.dts | 22 +
> .../dts/microchip/sparx5_pcb134_board.dtsi | 9 +
> .../boot/dts/microchip/sparx5_pcb135.dts | 23 +
> .../dts/microchip/sparx5_pcb135_board.dtsi | 9 +
> arch/mips/configs/generic/board-ocelot.config | 2 +-
> drivers/spi/Kconfig | 7 +
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++
> drivers/spi/spi-dw-mmio.c | 93 ----
> drivers/spi/spi-dw.c | 31 +-
> drivers/spi/spi-dw.h | 4 +
> 16 files changed, 644 insertions(+), 107 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> create mode 100644 drivers/spi/spi-dw-mchp.c
>
> --
> 2.26.2
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Serge Semin writes:
> Hello Lars,
>
> On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
>> This is an add-on series to the main SoC Sparx5 series
>> (Message-ID: <[email protected]>).
>>
>> The series add support for Sparx5 on top of the existing
>> ocelot/jaguar2 spi driver.
>>
>> It spins off the existing support for the MSCC platforms into a
>> separate driver, as adding new platforms from the MSCC/Microchip
>> product lines will further complicate (clutter) the original driver.
>>
>> New YAML dt-bindings are provided for the resulting driver.
>>
>> It is expected that the DT patches are to be taken directly by the arm-soc
>> maintainers.
>
> Regarding our cooperation. It can be implemented as follows. Since your patchset
> is less cumbersome than mine and is more ready to be integrated into the generic DW
> APB SSI code, it would be better to first make it through Mark', Andy' and my reviews
> to be further merged into the kernel version of the driver. After that I'll have
> my code altered so it could be applied on top of your patches. When everything
> is done we'll have a more comprehensive DW APB SSI driver with poll-based
> PIO operations support, new features like rx-delay, etc.
>
Hi Serge!
I think I would be able to work on the SPI patches this week. Should I
base it on the current spi-next or 5.7? Then address the comments and
send out a new revision?
Thanks for reaching out.
---Lars
> Thank you one more time for the series you've shared with us. Let's see what can
> be done to improve it...
>
> -Sergey
>
>>
>> Lars Povlsen (10):
>> spi: dw: Add support for polled operation via no IRQ specified in DT
>> spi: dw: Add support for RX sample delay register
>> spi: dw: Add support for client driver memory operations
>> dt-bindings: spi: Add bindings for spi-dw-mchp
>> spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
>> dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
>> spi: spi-dw-mchp: Add Sparx5 support
>> arm64: dts: sparx5: Add SPI controller
>> arm64: dts: sparx5: Add spi-nor support
>> arm64: dts: sparx5: Add spi-nand devices
>>
>> .../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++
>> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-
>> MAINTAINERS | 2 +
>> arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++
>> .../boot/dts/microchip/sparx5_pcb125.dts | 16 +
>> .../boot/dts/microchip/sparx5_pcb134.dts | 22 +
>> .../dts/microchip/sparx5_pcb134_board.dtsi | 9 +
>> .../boot/dts/microchip/sparx5_pcb135.dts | 23 +
>> .../dts/microchip/sparx5_pcb135_board.dtsi | 9 +
>> arch/mips/configs/generic/board-ocelot.config | 2 +-
>> drivers/spi/Kconfig | 7 +
>> drivers/spi/Makefile | 1 +
>> drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++
>> drivers/spi/spi-dw-mmio.c | 93 ----
>> drivers/spi/spi-dw.c | 31 +-
>> drivers/spi/spi-dw.h | 4 +
>> 16 files changed, 644 insertions(+), 107 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
>> create mode 100644 drivers/spi/spi-dw-mchp.c
>>
>> --
>> 2.26.2
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Lars Povlsen,
Microchip
On Tue, Jun 02, 2020 at 10:18:28AM +0200, Lars Povlsen wrote:
>
> Serge Semin writes:
>
> > Hello Lars,
> >
> > On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> >> This is an add-on series to the main SoC Sparx5 series
> >> (Message-ID: <[email protected]>).
> >>
> >> The series add support for Sparx5 on top of the existing
> >> ocelot/jaguar2 spi driver.
> >>
> >> It spins off the existing support for the MSCC platforms into a
> >> separate driver, as adding new platforms from the MSCC/Microchip
> >> product lines will further complicate (clutter) the original driver.
> >>
> >> New YAML dt-bindings are provided for the resulting driver.
> >>
> >> It is expected that the DT patches are to be taken directly by the arm-soc
> >> maintainers.
> >
> > Regarding our cooperation. It can be implemented as follows. Since your patchset
> > is less cumbersome than mine and is more ready to be integrated into the generic DW
> > APB SSI code, it would be better to first make it through Mark', Andy' and my reviews
> > to be further merged into the kernel version of the driver. After that I'll have
> > my code altered so it could be applied on top of your patches. When everything
> > is done we'll have a more comprehensive DW APB SSI driver with poll-based
> > PIO operations support, new features like rx-delay, etc.
> >
>
> Hi Serge!
>
> I think I would be able to work on the SPI patches this week. Should I
> base it on the current spi-next or 5.7? Then address the comments and
> send out a new revision?
>
> Thanks for reaching out.
Sorry for a delay. I had to finish urgent tasks first. I'll give my review comments
shortly today.
-Sergey
>
> ---Lars
>
> > Thank you one more time for the series you've shared with us. Let's see what can
> > be done to improve it...
> >
> > -Sergey
> >
> >>
> >> Lars Povlsen (10):
> >> spi: dw: Add support for polled operation via no IRQ specified in DT
> >> spi: dw: Add support for RX sample delay register
> >> spi: dw: Add support for client driver memory operations
> >> dt-bindings: spi: Add bindings for spi-dw-mchp
> >> spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
> >> dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
> >> spi: spi-dw-mchp: Add Sparx5 support
> >> arm64: dts: sparx5: Add SPI controller
> >> arm64: dts: sparx5: Add spi-nor support
> >> arm64: dts: sparx5: Add spi-nand devices
> >>
> >> .../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++
> >> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-
> >> MAINTAINERS | 2 +
> >> arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++
> >> .../boot/dts/microchip/sparx5_pcb125.dts | 16 +
> >> .../boot/dts/microchip/sparx5_pcb134.dts | 22 +
> >> .../dts/microchip/sparx5_pcb134_board.dtsi | 9 +
> >> .../boot/dts/microchip/sparx5_pcb135.dts | 23 +
> >> .../dts/microchip/sparx5_pcb135_board.dtsi | 9 +
> >> arch/mips/configs/generic/board-ocelot.config | 2 +-
> >> drivers/spi/Kconfig | 7 +
> >> drivers/spi/Makefile | 1 +
> >> drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++
> >> drivers/spi/spi-dw-mmio.c | 93 ----
> >> drivers/spi/spi-dw.c | 31 +-
> >> drivers/spi/spi-dw.h | 4 +
> >> 16 files changed, 644 insertions(+), 107 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> >> create mode 100644 drivers/spi/spi-dw-mchp.c
> >>
> >> --
> >> 2.26.2
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> [email protected]
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> Lars Povlsen,
> Microchip
On Tue, May 19, 2020 at 02:05:19PM +0200, Lars Povlsen wrote:
> On 13/05/20 16:18, Mark Brown wrote:
> > Date: Wed, 13 May 2020 16:18:11 +0100
> > From: Mark Brown <[email protected]>
> > To: Lars Povlsen <[email protected]>
> > Cc: SoC Team <[email protected]>, Microchip Linux Driver Support
> > <[email protected]>, [email protected],
> > [email protected], [email protected],
> > [email protected], Alexandre Belloni
> > <[email protected]>
> > Subject: Re: [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into
> > spi-dw-mchp
> > User-Agent: Mutt/1.10.1 (2018-07-13)
> >
> > On Wed, May 13, 2020 at 04:00:26PM +0200, Lars Povlsen wrote:
> >
> > > +config SPI_DW_MCHP
> > > + tristate "Memory-mapped io interface driver using DW SPI core of MSCC SoCs"
> > > + default y if ARCH_SPARX5
> > > + default y if SOC_VCOREIII
> >
> > Why the default ys?
>
> The SoC will typically boot from SPI... But its not a requirement per
> se. I will remove it.
>
> >
> > > +++ b/drivers/spi/Makefile
> > > @@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
> > > obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
> > > obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
> > > obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
> > > +obj-$(CONFIG_SPI_DW_MCHP) += spi-dw-mchp.o
> > > obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
> > > spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
> > > obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
> >
> > Please keep the file alphabetically sorted.
> >
>
> Noted.
>
> > > +++ b/drivers/spi/spi-dw-mchp.c
> > > @@ -0,0 +1,232 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Memory-mapped interface driver for MSCC SoCs
> > > + *
> >
> > Please make the entire comment a C++ one so things look more
> > intentional.
>
> Sure, I can do that. The presented form matches that of the other
> spi-dw-* drivers, but I can see other using // blocks. Ack.
>
> >
> > > +#define MAX_CS 4
> >
> > This should be namespaced.
>
> Ack.
>
> >
> > > + rx_sample_dly = 0;
> > > + device_property_read_u32(&pdev->dev, "spi-rx-delay-us", &rx_sample_dly);
> > > + dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly,
> > > + (dws->max_freq / 1000000));
Perhaps 100000 is better to be replace with macro USEC_PER_SEC...
Moreover are you sure the formulae is correct?
dws->rx_sample_dly - a number of ssi_clk periods/cycles to delay the Rx-data sample,
dws->max_freq - ssi_clk frequency (not period).
In real math the formulae would look like:
S = d * P [s], where d - number of delay cycles, P - ssi_clk period in seconds,
S - requested delay in seconds.
In the driver notation: d = dws->rx_sample_dly, P = 1 / dws->max_freq,
S = rx_sample_dly ("spi-rx-delay-us" property value).
dws->rx_sample_dly * (1 / dws->max_freq) = rx_sample_dly <=>
dws->rx_sample_dly = rx_sample_dly * dws->max_freq.
Though that's represented in seconds, so if rx_sample_dly is specified in usec,
then you'd need to scale it down dividing by USEC_PER_SEC.
For example, imagine we need a delay of 1 usec with ssi_clk of 50MHz.
By your formulae we'd have: 1 / (50000000 / 1000000) = 0 cycles (actually 1 due
to DIV_ROUND_UP, but incorrect anyway),
By mine: 1 * (500000000 / 1000000) = 50 cycles. Seems closer to reality.
Am I missing something?
> >
> > If this is a standard feature of the DesignWare IP why parse it here and
> > not in the generic code?
>
> This is a standard feature of the DesignWare IP, so good suggestion. I
> will arrange with Serge.
Regarding "spi-rx-delay-us" and the sampling delay the IP supports. Here is what
documentation says regarding the register, which is then initialized with this
parameter "This register controls the number of ssi_clk cycles that are
delayed from the default sample time before the actual sample of the rxd input
signal occurs." While the "spi-rx-delay-us" property is described as: "Delay, in
microseconds, after a read transfer." I may misunderstand something, but IMO
these descriptions don't refer to the same values. The only real use of the
"spi-rx-delay-us" property I've found in "./drivers/input/rmi4/rmi_spi.c".
That driver gets the value of the property and just sets the delay_usecs
of some transfers, which isn't even close to the functionality the RX_SAMPLE_DLY
register provides.
To be clear the RX_SAMPLE_DLY register can be used to delay the RX-bits sample
with respect to the normal Rx sampling timing. The delay is measured in the
numbers of the ssi_clk periods. (Note also that the maximum delay is limited
with a constant parameter pre-initialized at the IP-core synthesis stage. It can
be defined within a range [4, 255]. In our IP it's limited with just 4 periods.)
As I see it, a better way would be to either define a new vendor-specific
property like "snps,rx-sample-delay-ns" (note NS here, since normally the
ssi_clk is much higher than 1MHz), or define a new generic SPI property.
Mark, Andy?
-Sergey
>
> Thank you for your comments!
>
> ---Lars
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Wed, May 13, 2020 at 04:00:27PM +0200, Lars Povlsen wrote:
> This add DT bindings for the Sparx5 SPI driver.
This whole file can be easily merged in to the generic DW APB SSI DT
binding file. Just use "if: properties: compatible: const: ..." construction
to distinguish ocelot, jaguar, sparx5 and non-sparx5 nodes.
>
> Reviewed-by: Alexandre Belloni <[email protected]>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++----
> 1 file changed, 39 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> index a3ac0fa576553..8beecde4b0880 100644
> --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> @@ -23,15 +23,23 @@ properties:
> enum:
> - mscc,ocelot-spi
> - mscc,jaguar2-spi
> + - microchip,sparx5-spi
>
> interrupts:
> maxItems: 1
>
> reg:
> minItems: 2
> - items:
> - - description: Designware SPI registers
> - - description: CS override registers
> + maxItems: 3
> + oneOf:
> + - items:
> + - description: Designware SPI registers
> + - description: CS override registers (Not sparx5).
> + - items:
> + - description: Designware SPI registers
> + - description: CS override registers (Not sparx5).
> + - description: Direct mapped SPI read area. If provided, the
> + driver will register spi_mem_op's to take advantage of it.
>
> clocks:
> maxItems: 1
> @@ -43,6 +51,23 @@ properties:
> enum: [ 2, 4 ]
> maxItems: 1
>
> + spi-rx-delay-us:
> + description: |
> + The delay (in usec) of the RX signal sample position. This can
> + be used to tne the RX timing in order to acheive higher
> + speeds. This is used for all devices on the bus.
> + default: 0
> + maxItems: 1
spi-rx-delay-us is defined for a particular SPI-slave. Please see the
DT binding file: Documentation/devicetree/bindings/spi/spi-controller.yaml .
Although as I suggested before this delay isn't what the Dw APB SSI RX sample
delay functionality does. Probably a vendor-specific property would be better
here. But I'd also define it on a SPI-slave basis, not for all devices on the
bus.
> +
> + interface-mapping-mask:
> + description: |
> + On the Sparx5 variant, two different busses are connected to the
> + controller. This property is a mask per chip-select, indicating
> + whether the CS should go to one or the other interface.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + maxItems: 1
As Mark rightfully suggested this seems like an SPI-slave related property, then
most likely it should be defined on the SPI-slave basis (probably as a bool
property). Additionally it's vendor-specific, so the property name should be
accordingly prefixed.
> +
> required:
> - compatible
> - reg
> @@ -50,11 +75,15 @@ required:
>
> examples:
> - |
> - spi0: spi@101000 {
> - compatible = "mscc,ocelot-spi";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0x101000 0x100>, <0x3c 0x18>;
> - interrupts = <9>;
> - clocks = <&ahb_clk>;
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + spi0: spi@600104000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "microchip,sparx5-spi";
> + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>;
I have a doubt that defining an empty reg region is a good idea, since you can
detect the reg requirements by the node compatible string.
-Sergey
> + num-cs = <16>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> };
> --
> 2.26.2
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, Jun 02, 2020 at 10:18:28AM +0200, Lars Povlsen wrote:
>
> Serge Semin writes:
>
> > Hello Lars,
> >
> > On Wed, May 13, 2020 at 04:00:21PM +0200, Lars Povlsen wrote:
> >> This is an add-on series to the main SoC Sparx5 series
> >> (Message-ID: <[email protected]>).
> >>
> >> The series add support for Sparx5 on top of the existing
> >> ocelot/jaguar2 spi driver.
> >>
> >> It spins off the existing support for the MSCC platforms into a
> >> separate driver, as adding new platforms from the MSCC/Microchip
> >> product lines will further complicate (clutter) the original driver.
> >>
> >> New YAML dt-bindings are provided for the resulting driver.
> >>
> >> It is expected that the DT patches are to be taken directly by the arm-soc
> >> maintainers.
> >
> > Regarding our cooperation. It can be implemented as follows. Since your patchset
> > is less cumbersome than mine and is more ready to be integrated into the generic DW
> > APB SSI code, it would be better to first make it through Mark', Andy' and my reviews
> > to be further merged into the kernel version of the driver. After that I'll have
> > my code altered so it could be applied on top of your patches. When everything
> > is done we'll have a more comprehensive DW APB SSI driver with poll-based
> > PIO operations support, new features like rx-delay, etc.
> >
>
> Hi Serge!
>
> I think I would be able to work on the SPI patches this week. Should I
> base it on the current spi-next or 5.7? Then address the comments and
> send out a new revision?
Finally I've done a part of review. It must be enough for v2. As Mark said the
new version is supposed to be based on the spi-next, since that branch's got
all recent DW APB SSI patches applied.
-Sergey
>
> Thanks for reaching out.
>
> ---Lars
>
> > Thank you one more time for the series you've shared with us. Let's see what can
> > be done to improve it...
> >
> > -Sergey
> >
> >>
> >> Lars Povlsen (10):
> >> spi: dw: Add support for polled operation via no IRQ specified in DT
> >> spi: dw: Add support for RX sample delay register
> >> spi: dw: Add support for client driver memory operations
> >> dt-bindings: spi: Add bindings for spi-dw-mchp
> >> spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp
> >> dt-bindings: spi: spi-dw-mchp: Add Sparx5 support
> >> spi: spi-dw-mchp: Add Sparx5 support
> >> arm64: dts: sparx5: Add SPI controller
> >> arm64: dts: sparx5: Add spi-nor support
> >> arm64: dts: sparx5: Add spi-nand devices
> >>
> >> .../bindings/spi/mscc,ocelot-spi.yaml | 89 ++++
> >> .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-
> >> MAINTAINERS | 2 +
> >> arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++
> >> .../boot/dts/microchip/sparx5_pcb125.dts | 16 +
> >> .../boot/dts/microchip/sparx5_pcb134.dts | 22 +
> >> .../dts/microchip/sparx5_pcb134_board.dtsi | 9 +
> >> .../boot/dts/microchip/sparx5_pcb135.dts | 23 +
> >> .../dts/microchip/sparx5_pcb135_board.dtsi | 9 +
> >> arch/mips/configs/generic/board-ocelot.config | 2 +-
> >> drivers/spi/Kconfig | 7 +
> >> drivers/spi/Makefile | 1 +
> >> drivers/spi/spi-dw-mchp.c | 399 ++++++++++++++++++
> >> drivers/spi/spi-dw-mmio.c | 93 ----
> >> drivers/spi/spi-dw.c | 31 +-
> >> drivers/spi/spi-dw.h | 4 +
> >> 16 files changed, 644 insertions(+), 107 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml
> >> create mode 100644 drivers/spi/spi-dw-mchp.c
> >>
> >> --
> >> 2.26.2
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> [email protected]
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> Lars Povlsen,
> Microchip