This patch series is a stripped-down revision of the initial series
"[PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs":
https://lore.kernel.org/lkml/[email protected]/
At Stephen's request, I detached all DTS related work to keep the focus
exclusively on the Actions S500 SoC clock driver changes:
- Add support for some missing clocks: APB, DMAC, GPIO
- Add support for Reset Management Unit
The removed patches are subject to resubmission via a separate series:
- arm: dts: owl-s500: Add Clock Management Unit
- arm: dts: owl-s500: Set UART clock refs from CMU
- arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
- arm: dts: owl-s500: Add DMA controller
- arm: dts: owl-s500: Add Reset Controller support
Regards,
Cristi
Changes in v3:
- Incorporated feedback from Stephen and Mani
- Rebased on v5.8-rc3
Changes in v2:
- Incorporated Stephen's review comments
- Removed DTS related patches
- Rebased remaining patches on v5.8-rc2
- Updated cover letter, both subject and content, to reflect the new
scope
Cristian Ciocaltea (6):
clk: actions: Fix h_clk for Actions S500 SoC
dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
dt-bindings: reset: Add binding constants for Actions S500 RMU
clk: actions: Add Actions S500 SoC Reset Management Unit support
MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
MAINTAINERS | 1 +
drivers/clk/actions/owl-s500.c | 89 ++++++++++++++++++-
include/dt-bindings/clock/actions,s500-cmu.h | 7 +-
.../dt-bindings/reset/actions,s500-reset.h | 67 ++++++++++++++
4 files changed, 162 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
--
2.27.0
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.
Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v3:
- Added Fixes tag
- Added Mani's Reviewed-by tag
Changes in v2:
- None
drivers/clk/actions/owl-s500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index e2007ac4d235..0eb83a0b70bc 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
--
2.27.0
Add support for the missing APB, DMAC and GPIO clocks in the Actions
Semi S500 SoC clock driver.
Signed-off-by: Cristian Ciocaltea <[email protected]>
---
Changes in v3:
- None
Changes in v2:
- None
drivers/clk/actions/owl-s500.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 0eb83a0b70bc..025a8f6d6482 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -175,6 +175,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
/* gate clocks */
+static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
+static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
@@ -184,6 +186,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
@@ -428,6 +431,9 @@ static struct owl_clk_common *s500_clks[] = {
&spdif_clk.common,
&nand_clk.common,
&ecc_clk.common,
+ &apb_clk.common,
+ &dmac_clk.common,
+ &gpio_clk.common,
};
static struct clk_hw_onecell_data s500_hw_clks = {
@@ -484,6 +490,9 @@ static struct clk_hw_onecell_data s500_hw_clks = {
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_ECC] = &ecc_clk.common.hw,
+ [CLK_APB] = &apb_clk.common.hw,
+ [CLK_DMAC] = &dmac_clk.common.hw,
+ [CLK_GPIO] = &gpio_clk.common.hw,
},
.num = CLK_NR_CLKS,
};
--
2.27.0
Add device tree binding constants for Actions Semi S500 SoC Reset
Management Unit (RMU).
Signed-off-by: Cristian Ciocaltea <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
---
Changes in v3:
- Added Philipp's Acked-by tag
Changes in v2:
- None
.../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
new file mode 100644
index 000000000000..f5d94176d10b
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s500-reset.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Actions Semi S500 Reset Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2020 Cristian Ciocaltea <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
+#define __DT_BINDINGS_ACTIONS_S500_RESET_H
+
+#define RESET_DMAC 0
+#define RESET_NORIF 1
+#define RESET_DDR 2
+#define RESET_NANDC 3
+#define RESET_SD0 4
+#define RESET_SD1 5
+#define RESET_PCM1 6
+#define RESET_DE 7
+#define RESET_LCD 8
+#define RESET_SD2 9
+#define RESET_DSI 10
+#define RESET_CSI 11
+#define RESET_BISP 12
+#define RESET_KEY 13
+#define RESET_GPIO 14
+#define RESET_AUDIO 15
+#define RESET_PCM0 16
+#define RESET_VDE 17
+#define RESET_VCE 18
+#define RESET_GPU3D 19
+#define RESET_NIC301 20
+#define RESET_LENS 21
+#define RESET_PERIPHRESET 22
+#define RESET_USB2_0 23
+#define RESET_TVOUT 24
+#define RESET_HDMI 25
+#define RESET_HDCP2TX 26
+#define RESET_UART6 27
+#define RESET_UART0 28
+#define RESET_UART1 29
+#define RESET_UART2 30
+#define RESET_SPI0 31
+#define RESET_SPI1 32
+#define RESET_SPI2 33
+#define RESET_SPI3 34
+#define RESET_I2C0 35
+#define RESET_I2C1 36
+#define RESET_USB3 37
+#define RESET_UART3 38
+#define RESET_UART4 39
+#define RESET_UART5 40
+#define RESET_I2C2 41
+#define RESET_I2C3 42
+#define RESET_ETHERNET 43
+#define RESET_CHIPID 44
+#define RESET_USB2_1 45
+#define RESET_WD0RESET 46
+#define RESET_WD1RESET 47
+#define RESET_WD2RESET 48
+#define RESET_WD3RESET 49
+#define RESET_DBG0RESET 50
+#define RESET_DBG1RESET 51
+#define RESET_DBG2RESET 52
+#define RESET_DBG3RESET 53
+
+#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
--
2.27.0
On Fri, Jul 03, 2020 at 08:05:09PM +0300, Cristian Ciocaltea wrote:
> Add support for the missing APB, DMAC and GPIO clocks in the Actions
> Semi S500 SoC clock driver.
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Changes in v3:
> - None
>
> Changes in v2:
> - None
>
> drivers/clk/actions/owl-s500.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 0eb83a0b70bc..025a8f6d6482 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -175,6 +175,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
> static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
>
> /* gate clocks */
> +static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
> +static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
> static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
> static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
> static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
> @@ -184,6 +186,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>
> /* divider clocks */
> static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
> static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
>
> /* factor clocks */
> @@ -428,6 +431,9 @@ static struct owl_clk_common *s500_clks[] = {
> &spdif_clk.common,
> &nand_clk.common,
> &ecc_clk.common,
> + &apb_clk.common,
> + &dmac_clk.common,
> + &gpio_clk.common,
> };
>
> static struct clk_hw_onecell_data s500_hw_clks = {
> @@ -484,6 +490,9 @@ static struct clk_hw_onecell_data s500_hw_clks = {
> [CLK_SPDIF] = &spdif_clk.common.hw,
> [CLK_NAND] = &nand_clk.common.hw,
> [CLK_ECC] = &ecc_clk.common.hw,
> + [CLK_APB] = &apb_clk.common.hw,
> + [CLK_DMAC] = &dmac_clk.common.hw,
> + [CLK_GPIO] = &gpio_clk.common.hw,
> },
> .num = CLK_NR_CLKS,
> };
> --
> 2.27.0
>
On Fri, Jul 03, 2020 at 08:05:10PM +0300, Cristian Ciocaltea wrote:
> Add device tree binding constants for Actions Semi S500 SoC Reset
> Management Unit (RMU).
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Acked-by: Philipp Zabel <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Changes in v3:
> - Added Philipp's Acked-by tag
>
> Changes in v2:
> - None
>
> .../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
>
> diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
> new file mode 100644
> index 000000000000..f5d94176d10b
> --- /dev/null
> +++ b/include/dt-bindings/reset/actions,s500-reset.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Device Tree binding constants for Actions Semi S500 Reset Management Unit
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Copyright (c) 2020 Cristian Ciocaltea <[email protected]>
> + */
> +
> +#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
> +#define __DT_BINDINGS_ACTIONS_S500_RESET_H
> +
> +#define RESET_DMAC 0
> +#define RESET_NORIF 1
> +#define RESET_DDR 2
> +#define RESET_NANDC 3
> +#define RESET_SD0 4
> +#define RESET_SD1 5
> +#define RESET_PCM1 6
> +#define RESET_DE 7
> +#define RESET_LCD 8
> +#define RESET_SD2 9
> +#define RESET_DSI 10
> +#define RESET_CSI 11
> +#define RESET_BISP 12
> +#define RESET_KEY 13
> +#define RESET_GPIO 14
> +#define RESET_AUDIO 15
> +#define RESET_PCM0 16
> +#define RESET_VDE 17
> +#define RESET_VCE 18
> +#define RESET_GPU3D 19
> +#define RESET_NIC301 20
> +#define RESET_LENS 21
> +#define RESET_PERIPHRESET 22
> +#define RESET_USB2_0 23
> +#define RESET_TVOUT 24
> +#define RESET_HDMI 25
> +#define RESET_HDCP2TX 26
> +#define RESET_UART6 27
> +#define RESET_UART0 28
> +#define RESET_UART1 29
> +#define RESET_UART2 30
> +#define RESET_SPI0 31
> +#define RESET_SPI1 32
> +#define RESET_SPI2 33
> +#define RESET_SPI3 34
> +#define RESET_I2C0 35
> +#define RESET_I2C1 36
> +#define RESET_USB3 37
> +#define RESET_UART3 38
> +#define RESET_UART4 39
> +#define RESET_UART5 40
> +#define RESET_I2C2 41
> +#define RESET_I2C3 42
> +#define RESET_ETHERNET 43
> +#define RESET_CHIPID 44
> +#define RESET_USB2_1 45
> +#define RESET_WD0RESET 46
> +#define RESET_WD1RESET 47
> +#define RESET_WD2RESET 48
> +#define RESET_WD3RESET 49
> +#define RESET_DBG0RESET 50
> +#define RESET_DBG1RESET 51
> +#define RESET_DBG2RESET 52
> +#define RESET_DBG3RESET 53
> +
> +#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
> --
> 2.27.0
>
On Fri, 03 Jul 2020 20:05:10 +0300, Cristian Ciocaltea wrote:
> Add device tree binding constants for Actions Semi S500 SoC Reset
> Management Unit (RMU).
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Acked-by: Philipp Zabel <[email protected]>
> ---
> Changes in v3:
> - Added Philipp's Acked-by tag
>
> Changes in v2:
> - None
>
> .../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
>
Acked-by: Rob Herring <[email protected]>
Quoting Cristian Ciocaltea (2020-07-03 10:05:07)
> The h_clk clock in the Actions Semi S500 SoC clock driver has an
> invalid parent. Replace with the correct one.
>
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> ---
Applied to clk-next
Quoting Cristian Ciocaltea (2020-07-03 10:05:09)
> Add support for the missing APB, DMAC and GPIO clocks in the Actions
> Semi S500 SoC clock driver.
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> ---
Applied to clk-next
Quoting Cristian Ciocaltea (2020-07-03 10:05:10)
> Add device tree binding constants for Actions Semi S500 SoC Reset
> Management Unit (RMU).
>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Acked-by: Philipp Zabel <[email protected]>
> ---
Applied to clk-next